Semiconductor integrated circuit device

• US 6,314,044 B1
• Filed: 06/15/2000
• Issued: 11/06/2001
• Est. Priority Date: 10/02/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Sasaki, Toshio, Sato, Jun, Miyamoto, Takashi, Yanagisawa, Kazumasa, Ayukawa, Kazushige, Tanaka, Yuji, Tanaka, Hitoshi, Nakanishi, Satoru, Watanabe, Takao, Ohtsuka, Mariko
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/594,840
• Time in Patent Office: 509 Days
• Field of Search: 365/230.03, 365/230.06, 365/230.02, 365/200
• US Class Current: 365/230.03
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

Claims

1. A semiconductor memory device comprising:

a plurality of arithmetic circuits which are connected in cascade form; and

a plurality of comparators, each of which determine coincidence between an address signal and either one of an input signal supplied to a corresponding one of said arithmetic circuits or an output signal produced therefrom;

further comprising a plurality of circuits coupled to said comparators,

wherein one of said circuits is activated when a corresponding one of said comparators shows coincidence.

2. A semiconductor integrated circuit device comprising:

a plurality of arithmetic circuits which are connected in series; and

a comparison circuit which determines coincidence between one of input signals of said plurality of arithmetic circuits and an address signal,

wherein each of said arithmetic circuits forms an output signal to be supplied to a successive arithmetic circuit.

3. A semiconductor memory device according to claim 2, further comprising:

a plurality of circuit blocks,

wherein one of said circuit blocks is activated when one of said input signals of a corresponding one of said arithmetic circuits is coincident with said address signal.

4. A semiconductor of integrated circuit device comprising:

a plurality of arithmetic circuits which are connected in series; and

a comparison circuit which determines coincidence between one of output signals of said plurality of arithmetic circuits and an address signal,

wherein each of said arithmetic circuits forms an output signal to be supplied to a successive arithmetic circuit.

5. A semiconductor memory device according to claim 4, further comprising:

a plurality of circuit blocks,

wherein one of said circuit blocks is activated when one of said output signals of a corresponding one of said arithmetic circuits is coincident with said address signal.

6. A semiconductor integrated circuit device comprising:

a plurality of arithmetic circuits which are connected in series;

a plurality of comparators, each of which determine coincidence between an address signal and either one of an input signal supplied to a corresponding one of said arithmetic circuits or an output signal produced therefrom; and

a plurality of memory arrays;

wherein one of said memory arrays is activated when a corresponding one of said comparators shows coincidence.