Low cost alternative to large dual port RAM

• US 6,314,047 B1
• Filed: 11/15/2000
• Issued: 11/06/2001
• Est. Priority Date: 12/30/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Keay, John, Robertson, Iain, Guttag, Karl M., Balmer, Keith
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/713,560
• Time in Patent Office: 356 Days
• Field of Search: 365/230.05, 365/189.01, 365/189.02, 365/221, 365/230.02, 365/189.04, 365/230.08, 365/189.05
• US Class Current: 365/230.05
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.

Claims

1. A method of implementing a dual port function employing a single port memory having a command, write data and address input and a read data output comprising the steps of:

receiving memory access requests on a first port and a second port;

servicing a received memory access from either requesting port via the single port memory by connecting said requesting port to the single port memory if only one port requests memory access;

buffering a memory access request received from said first port in a request first-in-first-out memory if said request first-in-first-out memory is not full and memory access requests are received from both said first port and said second port;

stalling a memory access request received from said second port and connecting a first entered memory access request buffered in said request first-in-first-out memory to the single port memory if said request first-in-first-out memory is full and a memory access request is received from said second port; and

connecting a first entered memory access request buffered in said request first-in-first-out memory to the single port memory if said request first-in-first-out memory is not empty and no memory access request is received from said second port.

2. The method of claim 1, further comprising the step of:

buffering read data from the read data output of the single port memory recalled in response to a read memory access request received from said first port in a read data first-in-first-out memory before supply to said first port to achieve a fixed latency equal to the depth of said request first-in-first-out memory from receipt of a read memory access request from said first port until supply of read data to said first port.

3. The method of claim 1, further comprising the step of:

buffering a memory access request received from said first port in said request first-in-first-out memory and connecting a first entered memory access request buffered in said request first-in-first-out memory to the single port memory if said request first-in-first-out memory is not empty.

4. The method of claim 1, wherein the single port memory is constructed of plural memory banks and further comprising the steps of:

determining from an address of a memory access request received from said first port and said second port a one of the plural memory banks addressed; and

wherein said steps of servicing a received memory access, buffering a memory access request received from said first port, stalling a memory access request received from said second port and connecting a first entered memory access request buffered in said request first-in-first-out memory to the single port memory are performed for each of said plural memory banks with respect to memory access request directed to the corresponding memory bank.

5. The method of claim 1, further comprising the step of:

detecting whether a read memory access request received from said second port specifies a read address equal to a write address of a write memory access request buffered in said request first-in-first-out memory; and

upon detecting a read memory access request received from said second port specifies a read address equal to a write address of a write memory access request buffered in said request first-in-first-out memory stalling said second port and connecting a first entered memory access request buffered in said request first-in-first-out memory to the single port memory until said write memory access request is connected to the single port memory.

6. The method of claim 1, further comprising the step of:

detecting whether a read memory access request received from said second port specifies a read address equal to a write address of a write memory access request buffered in said request first-in-first-out memory; and

upon detecting a read memory access request received from said second port specifies a read address equal to a write address of a write memory access request buffered in said request first-in-first-out memory supplying read data to said second port equal to said write data of said write memory access request buffered in said request memory first-in-first-out memory.

7. The method of claim 1, wherein the single port memory is constructed of plural memory banks and further comprising the steps of:

determining from an address of any memory access request received from said first port and from said second port a one of the plural memory banks addressed; and

wherein said steps of servicing a received memory access, buffering a read memory access request received from said first port in said read request first-in-first-out memory, stalling a memory access request received from said second port and connecting a first entered memory access request buffered in said read request first-in-first-out memory to the single port memory, connecting a first entered read memory access request buffered in said read request first-in-first-out memory to the single port memory, buffering a write memory access request received from said first port in a write request first-in-first-out memory, connecting a first entered write memory access request buffered in said write request first-in-first-out memory to the single port memory and buffering read data from the read data output of the single port memory are performed for each of said plural memory banks with respect to memory access request directed to the corresponding memory bank.

8. A method of implementing a dual port function employing a single port memory having a command, write data and address input and a read data output comprising the steps of:

receiving memory access requests on a first port and a second port;

servicing a received memory access from either requesting port via the single port memory by connecting said requesting port to the single port memory if only one port requests memory access;

buffering a read memory access request received from said first port in a read request first-in-first-out memory if said read request first-in-first-out memory is not full and a read memory access request is received said first port and a memory access request is receive from said second port;

stalling a memory access request received from said second port and connecting a first entered memory access request buffered in said read request first-in-first-out memory to the single port memory if said read request first-in-first-out memory is full and a memory access request is received from said second port;

connecting a first entered read memory access request buffered in said read request first-in-first-out memory to the single port memory if said read request first-in-first-out memory is not empty and a memory access request is not received from said second port;

buffering a write memory access request received from said first port in a write request first-in-first-out memory if said write request first-in-first-out memory is not full and a memory access request is received from said second port;

connecting a first entered write memory access request buffered in said write request first-in-first-out memory to the single port memory if said write request first-in-first-out memory is not empty and no memory access request is received from said second port; and

buffering read data from the read data output of the single port memory recalled in response to a memory access request received from said first port in a read data first-in-first-out memory before supply to said first port to achieve a fixed latency equal to the depth of said read request first-in-first-out memory from receipt of a read memory access request from said first port until supply of read data to said first port.

9. The method of claim 8, further comprising the step of:

buffering a read memory access request received from said first port in said read request first-in-first-out memory and connecting a first entered read memory access request buffered in said read request first-in-first-out memory to the single port memory if said read request first-in-first-out memory is not empty.

10. The method of claim 8, further comprising the step of:

buffering a write memory access request received from said first port in said write request first-in-first-out memory and connecting a first entered write memory access request buffered in said write request first-in-first-out memory to the single port memory if said write request first-in-first-out memory is not empty and no memory access request is received from said second port.

11. The method of claim 8, further comprising the step of:

detecting whether a read memory access request received from said second port specifies a read address equal to a write address of a write memory access request buffered in said write request first-in-first-out memory; and

upon detecting a read memory access request received from said second port specifies a read address equal to a write address of a write memory access request buffered in said write request first-in-first-out memory stalling said second port and connecting a first entered memory access request buffered in said write request first-in-first-out memory to the single port memory until said write memory access request is connected to the single port memory.

12. The method of claim 8, further comprising the step of:

detecting whether a read memory access request received from said second port specifies a read address equal to a write address of a write memory access request buffered in said write request first-in-first-out memory; and

upon detecting a read memory access request received from said second port specifies a read address equal to a write address of a write memory access request buffered in said write request first-in-first-out memory supplying read data to said second port equal to said write data of said write memory access request buffered in said write request memory first-in-first-out memory.

13. A memory controller comprising:

a single port memory having a command/write data/address input and a read data output;

a first port receiving first command, first write data and first address from a first memory requestor node and supplying read data from said read output of said single port memory to said first memory requester;

a second port receiving second command, second write data and second address from a second memory requester node and supplying read data from said read output of said single port memory to said second memory requester;

a command/write data/address first-in-first-out buffer having an input receiving said first command, said first write data and said first address from said first port, and having an output;

a command/write data/address multiplexer having a first input connected to said output of said command/write data/address first-in-first-out buffer, a second input receiving said first command, said first write data and said first address from said first port and an output;

a port multiplexer having first input connected to said output of said command/write data/address multiplexer, a second input receiving said second command, said second write data and said second address from said second port and an output connected to said command/write data/address input of said single port memory; and

a memory controller connected to said command/write data/address multiplexer and said port multiplexer, said memory controller controlling said command/write data/address multiplexer and said port multiplexer to

select said second input of said port multiplexer to connect a memory access request received from said second port to said single port memory if a memory access request is received from said second port, a memory access request is not received from said first port and said command/write data/address first-in-first-out buffer is empty,

select said second input to said command/write data/address multiplexer and said first input of said port multiplexer to connect a memory access request received from said first port to said single port memory if a memory access request is received from said first port, a memory access request is not received from said second port and said command/write data/address first-in-first-out buffer is empty,

select said first input to said command/write data/address multiplexer and said first input of said port multiplexer to connect a memory access request stored in said command/write data/address to said single port memory if a memory access request is not received from said second port and said command/write data/address first-in-first-out buffer is not empty, and

select said first input to said command/write data/address multiplexer and said first input of said port multiplexer to connect a memory access request stored in said command/write data/address to said single port memory and sending a stall signal to said second port if a memory access request is received from said first port, a memory access request is received from said second port and said command/write data/address first-in-first-out buffer is full.

14. The memory controller of claim 13, further comprising:

a read data first-in-first-out buffer having an input connected to said read data output of said single port memory and an output;

a read data multiplexer having a first input connected to said read data output of said single port memory, a second input connected to said output of said read data first-in-first-out buffer and an output supplying read data to said first port; and

wherein said memory controller is further connected to said read data multiplexer to control said read data multiplexer to achieve a fixed latency equal to the depth of said command/write data/address first-in-first-out buffer of a read memory access request from said first port until supply of read data to said first port.