Memory device having write latency

• US 6,314,051 B1
• Filed: 07/31/2000
• Issued: 11/06/2001
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US09/629,497
• Time in Patent Office: 463 Days
• Field of Search: 365/233, 365/194, 365/233.5
• US Class Current: 365/233.1
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to a write request, a first portion of data after a number of clock cycles of the external clock signal transpire. The first portion of data is sampled synchronously with respect to the external clock signal.

Claims

1. A memory device having a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive an external clock signal; and

input receiver circuitry to sample, in response to an operation code specifying a write operation, a first portion of data after a number of clock cycles of the external clock signal transpire, wherein the input receiver circuitry samples the first portion of data synchronously with respect to the external clock signal.

2. The memory device of claim 1 wherein the number of clock cycles transpire after receiving the operation code.

3. The memory device of claim 1 wherein the number of clock cycles of the external clock signal is fixed.

4. The memory device of claim 1 wherein the number of clock cycles of the external clock signal is programmable after power is applied to the memory device.

5. The memory device of claim 4 further including a programmable register to store a value representative of the number of clock cycles of the external clock signal.

6. The memory device of claim 1 wherein the input receiver circuitry samples a second portion of data synchronously with respect to the external clock signal, and wherein the input receiver circuitry samples the first portion of data in response to a rising edge transition of the external clock signal and the input receiver circuitry samples the second portion of data in response to a falling edge transition of the external clock signal.

7. The memory device of claim 1 further including a clock alignment circuit, coupled to the clock receiver circuitry, to generate an internal clock signal using the external clock signal.

8. The memory device of claim 1 further including a delay lock loop circuit, coupled to the clock receiver circuitry, to generate an internal clock signal using the external clock signal.

9. The memory device of claim 8 wherein the number of clock cycles is defined by a binary value which is stored in the memory device after power is applied to the memory device.

10. The memory device of claim 1 wherein the plurality of memory cells are dynamic random access memory cells.

11. The memory device of claim 1 wherein the input receiver circuitry and the clock receiver circuitry are coupled to an external bus.

12. The memory device of claim 11 wherein the external bus includes a plurality of signal lines to multiplex data, control information and address information.

13. The memory device of claim 11 wherein the input receiver circuitry samples address information on the external bus synchronously with respect to the external clock signal.

14. A memory device having a plurality of memory cells, the memory device comprising:

first input receiver circuitry to receive an operation code, wherein in response to the operation code, the memory device performs a write operation; and

second input receiver circuitry to sample data, in response to the operation code, after a predetermined delay time transpires.

15. The memory device of claim 14 further including third input receiver circuitry to receive address information.

16. The memory device of claim 14 wherein the predetermined delay time is representative of a number of clock cycles of an external clock signal to transpire.

17. The method of claim 14 wherein the data is received from an external bus.

18. The memory device of claim 17 wherein the external bus includes a plurality of signal lines to multiplex control information, address information and the data.

19. The memory device of claim 14 wherein the second input receiver circuitry samples a first portion of the data in response to a rising edge transition of an external clock signal and samples a second portion of the data in response to a falling edge transition of the external clock signal.

20. The memory device of claim 14 further including a programmable register to store a value which is representative of the predetermined delay time.

21. The memory device of claim 14 further including:

a clock receiver circuit to receive an external clock signal; and

a clock alignment circuit coupled to the clock receiver circuit, to generate an internal clock signal having a predetermined timing relationship with respect to the external clock signal, wherein the first input receiver circuitry samples the operation code in response to the internal clock signal.

22. The memory device of claim 14 further including:

a clock receiver circuit to receive an external clock signal; and

a delay lock loop circuit, coupled to the clock receiver circuit, to generate an internal clock signal having a predetermined timing relationship with respect to external clock signal.

23. The memory device of claim 22 wherein the second input receiver circuitry samples a first portion of the data in response to the internal clock signal.

24. The memory device of claim 14 wherein the first input receiver circuitry and the second input receiver circuitry are coupled to an external bus.

25. The memory device of claim 24 wherein the first input receiver circuitry and the second input receiver circuitry are coupled to the same set of external signal lines.

26. The memory device of claim 25 wherein control information and the data are multiplexed over the same set of external signal lines.

27. A memory device having a plurality of memory arrays, wherein each memory array includes a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive an external clock signal;

a programmable register to store a value which is representative of a number of clock cycles of the external clock signal to transpire before sampling a first portion of data, wherein the first portion of data is sampled in response to an operation code; and

data input receiver circuitry to sample the first portion of data synchronously with respect to the external clock signal.

28. The memory device of claim 27 wherein the data input receiver samples a second portion of data synchronously with respect to the external clock signal, and wherein the data input receiver samples the first portion of data in response to a rising edge transition of the external clock signal and samples the second portion of data in response to a falling edge transition of the external clock signal.

29. The memory device of claim 28 further including:

a delay lock loop circuit, coupled to the clock receiver circuitry;

a first latch, coupled to the delay lock loop, to sample the data in response to the rising edge transition of the external clock signal; and

a second latch, coupled to the delay lock loop, to sample the data in response to the falling edge transition of the external clock signal.

30. The memory device of claim 27 wherein the data input receiver circuitry includes a plurality of input receivers coupled to an external bus wherein the external bus includes a plurality of signal lines for carrying multiplexed data, control information and address information.

31. The memory device of claim 27 wherein the value is a binary representation of a number of clock cycles of the external clock signal.

32. The memory device of claim 27 further including a clock alignment circuit coupled to the clock receiver circuitry, to generate an internal clock signal having a predetermined phase relationship with respect to the external clock signal.

33. The memory device of claim 32 wherein the clock alignment circuit is a delay lock loop circuit.

34. A memory device having a plurality of memory arrays, the memory device comprising:

first input receiver circuitry to receive an operation code synchronously with respect to an external clock; and

second input receiver circuitry to sample data, in response to the operation code, after a predetermined number of clock cycles of the external clock.

35. The memory device of claim 34 further including:

a clock receiver circuit to receive the external clock;

a delay lock loop circuit, coupled to the clock receiver circuit, to generate an internal clock signal having a predetermined timing relationship with respect to external clock.

36. The memory device of claim 35 further including:

a first latch, coupled to receive the internal clock signal, wherein, in response to the internal clock signal, the first latch samples the data.

37. The memory device of claim 34 further including:

a delay lock loop circuit coupled to the clock receiver circuitry;

a first latch, coupled to the delay lock loop circuit, to sample data in response to the rising edge transition of the external clock; and

a second latch, coupled to the delay lock loop circuit, to sample data in response to the falling edge transition of the external clock.

38. The memory device of claim 34 further including a programmable register to store a value which is representative of the predetermined number of clock cycles of the external clock.

39. The memory device of claim 38 wherein the value which is representative of the predetermined number of clock cycles of the external clock is stored in the programmable register after power is applied to the memory device.

40. The memory device of claim 34 wherein the first input receiver circuitry includes a plurality of input receivers coupled to an external bus wherein the external bus includes a plurality of signal lines for carrying multiplexed data, control information and address information.

41. The memory device of claim 34 wherein the predetermined number of clock cycles of the external clock is fixed.

42. The memory device of claim 34 wherein the first input receiver circuitry and the second input receiver circuitry are coupled to an external bus.

43. The memory device of claim 34 wherein the memory device is a synchronous dynamic random access memory.