Performance of fibre channel protocol sequence reassembly using expected frame information and buffer list calculations

• US 6,314,477 B1
• Filed: 10/30/1998
• Issued: 11/06/2001
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Microsemi Solutions (U.S.), Inc. (Microchip Technology Incorporated)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Steinmetz, Joseph H, Wakeley, Matthew P, Cowger, Bryan J, Mathew, Brandon H
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/183,865
• Time in Patent Office: 1,103 Days
• Field of Search: 710/22, 710/23, 710/52, 709/236, 370/394
• US Class Current: 710/22
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9052 with buffers of different sizes
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

A method and system, implemented in hardware, for quickly and efficiently reassembling Fibre Channel data sequence data received by a Fibre Channel port in host memory buffers. The host memory buffers are referenced by a transaction status block allocated and initialized by the host. The transaction status block is referenced by the Fibre Channel port during transfer of data received in each Fibre Channel data frame of the Fibre Channel data sequence. The host memory buffers may be or arbitrary size and need only be byte aligned. The host computer can specify any number of host memory buffers by appropriate initialization of the transaction status block.

Claims

1. An interface controller that operates together with a communications network host to implement a number of network communications protocol layers, the interface controller coupled to a receiver that is, in turn, coupled to a communications network transport medium through which the receiver receives a data sequence, the data sequence composed of a number of data frames that contain data, the interface controller comprising:

a direct memory access engine for transferring data from a received data frame to a host memory buffer;

a transaction status block allocated within host memory and initialized by the host to represent a data sequence, the transaction status block containing information fields and referencing a number of arbitrarily-sized and byte-aligned host memory buffers; and

a logic component that assembles data, received in data frames, in host memory, sequentially ordering the data according to an order specified by the data sequence, processing each data frame received by the receiver, both in the case that the data frame is received in-order with respect to the data sequence and in the case that the data frame is received out-of-order with respect to the data sequence, by directing the direct memory access engine to transfer one or more data blocks from the received data frame into one or more locations within one or more host memory buffers, the number of data block transfers depending on the relative sizes of the data to be transferred and the available space remaining in the host memory buffer to which the data is transferred, the logic component determining a host memory buffer and location within the host memory buffer into which to transfer a data block by using the information fields and host memory buffer references contained in the transaction status block.

2. The interface controller of claim 1 wherein the transaction status block contains an expected relative offset information field and each data frame includes an indication of the relative offset of the data contained in the data frame with respect to the data sequence, wherein the expected relative offset information field indicates the relative offset that should be included in the sequential next data frame of the data sequence, and wherein the interface controller determines, by comparing the relative offset included in a received data frame to the expected relative offset information field, whether the received data fame was received in order with respect to the data sequence.

3. The interface controller of claim 2 wherein the transaction status block contains buffer index and buffer offset information fields and wherein the interface controller, upon determining that a received data frame has been received in order with respect to the data sequence, determines a host memory buffer into which to transfer a first block of data from the received data frame from a value contained in the buffer index information field and determines the location within the determined host memory buffer into which to transfer a first block of data from the received data frame from a value contained in the buffer offset information field.

4. The interface controller of claim 3 used to implement a Fibre Channel port, wherein the data sequence is a Fibre Channel sequence composed of a number of Fibre Channel data frames.

5. The interface controller of claim 4 wherein the transaction status block contains data fields containing references to host memory buffers.

6. The interface controller of claim 4 wherein the transaction status block may contain a data field containing a reference to a linked list of auxiliary blocks that each contain references to host memory buffers.

7. A method for placing data in a received data frame of a data sequence by an interface controller, operating in a network communication port that interfaces a communications network with a host, into a position within host memory specified by the data sequence according to a network communications protocol so that the interface controller assembles data received in all data frames of a data sequence sequentially within one or more host memory buffers allocated by the host, the method comprising:

receiving from the received data frame an indication of the relative offset of the data contained in the received data frame with respect to the data sequence;

comparing the received indication of the relative offset of the data contained in the received data frame to an expected relative offset to determine whether the received data frame has been received in-order with respect to the data sequence;

when the received data frame has been received in-order with respect to the data sequence,

using a stored indication of a host memory buffer and a stored indication of an offset within the host memory buffer to calculate a size of a first data block to transfer from the received data frame to the host memory buffer, and

transferring the first data block from the received data frame to the host memory buffer starting at the indicated offset within the indicated host memory buffer; and

when the received data frame has not been received in-order with respect to the data sequence,

determining a size of a first data block in the received data frame, a host memory buffer, and an offset within the host memory buffer into which to transfer the first data block in the received data frame to the host memory buffer by examining stored references to successive host memory buffers, and

transferring the first data block from the received data frame to the determined host memory buffer starting at the determined offset within the determined host memory buffer.

8. The method of claim 7 further including:

after transferring the first data block, repeatedly

determining whether there is an additional next data block within the received data frame that needs to be transferred to a host memory buffer; and

if there is an additional next data block within the received data frame that needs to be transferred to a host memory buffer,

determining a size of the next data block, a next host memory buffer, and a next offset within the next host memory buffer into which to transfer the next data block by examining a stored reference to a first host memory buffer reference containing available memory, and

transferring the next data block from the received data frame to the determined the next host memory starting at the determined next offset within the determined next host memory buffer;

until there is no additional next data block within the received data frame that needs to be transferred to a host memory buffer.

9. The method of claim 8 wherein the interface controller is used to implement within a Fibre Channel port.

10. The method of claim 9 wherein the interface controller is used to implement a Fibre Channel port within a Fibre Channel arbitrated loop topology.

11. The method of claim 10 wherein determining a size of a first data block in the received data frame, a host memory buffer, and an offset within the host memory buffer into which to transfer the first data block in the received data frame to the host memory buffer by examining stored references to successive host memory buffers further includes:

examining references stored in transaction status block allocated and intialized by the host.

12. The method of claim 10 wherein determining a size of a first data block in the received data frame, a host memory buffer, and an offset within the host memory buffer into which to transfer the first data block in the received data frame to the host memory buffer by examining stored references to successive host memory buffers further includes:

examining references stored in a linked list of auxiliary data structures referenced from a transaction status block, the linked list of auxiliary data structures and the transaction status block allocated and initialized by the host.

13. The method of claim 10 wherein determining a size of the next data block, a next host memory buffer, and a next offset within the next host memory buffer into which to transfer the next data block by examining a stored reference to a first host memory buffer reference containing available memory further includes:

examining a reference to a first host memory buffer reference containing available memory stored in transaction status block allocated and intialized by the host.

14. The method of claim 10 wherein determining a size of the next data block, a next host memory buffer, and a next offset within the next host memory buffer into which to transfer the next data block by examining a stored reference to a first host memory buffer reference containing available memory further includes:

examining a reference to a first host memory buffer reference containing available memory stored in a linked list of auxiliary data structures referenced from a transaction status block, the linked list of auxiliary data structures and the transaction status block allocated and initialized by the host.

15. A fibre channel interface controller included within a fibre channel port that operates together with a host as a fibre channel node, the fibre channel interface controller including:

an inbound buffer in which received fibre channel data frames are buffered;

a transaction status block allocated within host memory and initialized by the host to represent a data sequence composed of sequentially ordered data included in a set of sequentially ordered fibre channel data frames, the transaction status block containing information fields and referencing a number of arbitrarily-sized and byte-aligned host memory buffers that together define a logical sequence of host memory positions into which the fibre channel interface controller transfers the sequentially ordered data of the data sequence;

a memory transfer engine that transfers data from a fibre channel frame stored in the inbound buffer to a position within the logical sequence of host memory positions; and

a logic circuit that determines, based on information contained in a received data frame and information contained in the transaction status block, a position within the logical sequence of host memory positions to which to direct the memory transfer engine to transfer data in the received data frame so that the data is placed in a position in the logical sequence of host memory positions corresponding to the position of the data within the data sequence.

16. The interface controller of claim 15 wherein the transaction status block contains an expected relative offset information field and each data frame includes an indication of the relative offset of the data contained in the data frame with respect to the data sequence.