Processor having a trace access instruction to access on-chip trace memory
First Claim
1. A method of operating a computer system including a processor, comprising:
- said processor executing a trace access instruction stored in a memory for storing instructions executable by said processor, to access an on-chip trace memory on said processor, said trace memory having a plurality of locations for storing trace information indicative of execution flow of a plurality of said instructions in said processor.
3 Assignments
0 Petitions
Accused Products
Abstract
A computer system includes a memory for storing instructions executable by a processor and an on-chip trace memory having a plurality of locations for storing trace information that indicates execution flow in the processor. A trace access instruction provides for access to the on-chip trace memory on the processor. The trace access instruction can be a write instruction or a read instruction. Typically, both read and write to the trace memory is provided. The system also has the capability to trace on start or restart of an executable thread by providing to the processor an indication of which executable thread to trace via a debug port. That indicates to the processor to provide trace information when the executable thread starts. When execution of the executable thread starts, the processor places an identifier corresponding to the executable thread into the trace memory to indicate that subsequent entries placed into the trace memory are part of said executable thread. The processor may also provide an entry indicating when the thread stops executing.
385 Citations
36 Claims
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1. A method of operating a computer system including a processor, comprising:
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said processor executing a trace access instruction stored in a memory for storing instructions executable by said processor, to access an on-chip trace memory on said processor, said trace memory having a plurality of locations for storing trace information indicative of execution flow of a plurality of said instructions in said processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 34, 35, 36)
providing to said processor an indication to trace on execution of an executable thread thereby indicating to said processor to provide trace information when said executable thread executes;
starting execution of said executable thread; and
providing an identifier corresponding to said executable thread into said trace memory to indicate that subsequent entries placed into said trace memory are part of said executable thread.
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7. The method as recited in claim 6 wherein providing said identifier uses said trace access instruction to write said identifier into said trace memory.
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8. The method as recited in claim 6 further comprising the processor placing trace information into said trace memory reflecting instruction execution flow in said executable thread.
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9. The method as recited in claim 8 further comprising stopping placing said trace information into said trace memory in response to execution of said executable thread being stopped.
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10. The method as recited in claim 6 further comprising:
writing a code associated with said identifier into said trace memory to indicate that data in said trace memory associated with said code is said identifier.
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11. The method as recited in claim 10 wherein a portion of a record in said trace memory is reserved for writing said identifier, write access to said portion of said record requiring a predetermined system privilege level.
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12. The method as recited in claim 6 wherein a debug host provides said processor with said indication to trace on execution of said executable thread, via a debug port on said processor.
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13. The method as recited in claim 6 wherein said executable thread is one of a task and a thread.
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14. The method as recited in claim 1 further comprising:
storing trace information into said trace memory prior to said trace access instruction when code is executing at a first privilege level, and stopping storing into said trace memory when code is executed at a second privilege level.
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15. The method as recited in claim 14 wherein said first privilege level is of an application task and said second privilege level being of a system task.
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16. The method as recited in claim 2 wherein said data written into said trace memory is a time stamp.
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17. The method as recited in claim 2 wherein said data written into said trace memory is a state of a hardware peripheral device.
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34. The method as recited in claim 1 wherein said trace access instruction is a write instruction and said write instruction writes data stored in a processor register to said trace memory.
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35. The method as recited in claim 4 wherein said data read from one of said locations in said trace memory is stored into a processor register as a result of execution of said read instruction.
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36. The method as recited in claim 4 wherein said data read from one of said locations in said trace memory is stored in a location determined by said read instruction.
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18. A computer program embodied on computer readable media, for execution on a computer system including a processor, said processor including an on-chip trace memory, and a memory for storing instructions executable by said processor, the computer program comprising:
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a trace access instruction executable by said processor, to access said trace memory on said processor, said trace memory having a plurality of locations for storing trace information indicative of instruction execution flow in said processor. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
a control segment maintaining a first identifier associated with an executable thread, said executable thread for execution on said processor;
a scheduler segment for starting execution of said executable thread;
wherein said computer program writes a second identifier, corresponding to said first identifier, into said trace memory to indicate that subsequent entries to said trace memory are part of said executable thread.
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24. The computer program as recited in claim 23 wherein said computer program is a component of a multi-tasking operating system.
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25. The computer program as recited in claim 24 wherein said executable thread is part of an application software program different from said operating system.
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26. A method of operating a computer system including a processor and a memory storing instructions for said processor, the method comprising:
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identifying an executable thread to trace as a first trace condition;
in response to said identifying step, storing an indicator that said executable thread is to be traced;
providing additional trace control information indicating when to enable tracing instruction execution flow within said executable thread, as a second trace condition; and
providing trace information indicating instruction execution flow when said first and second trace conditions are both true. - View Dependent Claims (27, 28, 29, 30)
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31. An operating system including a trace handling component, said operating system for execution on a computer system including a processor and memory for storing instructions executable by said processor, the trace handling component comprising:
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a trace read instruction for accessing an on-chip trace memory on said processor, said trace read instruction being stored in said memory, said trace memory having a plurality of locations for storing trace information indicative of instruction execution flow in said processor; and
a trace write instruction, said trace write instruction writing data identified by said trace write instruction to one of said locations in said trace memory. - View Dependent Claims (32, 33)
control software maintaining a first identifier associated with one of a task and an executable thread, said executable thread for execution on said processor;
scheduler software for starting execution of said executable thread; and
wherein said computer program writes a second identifier, corresponding to said first identifier, into said trace memory to indicate that subsequent entries into said trace cache are part of said executable thread.
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33. The operating system as recited in claim 32 wherein said second identifier is the same as said first identifier.
Specification