Interconnect capacitive effects estimation
First Claim
1. A method for estimating interconnect capacitive effects, comprising:
- modeling a gate; and
estimating an effective capacitance that models the interconnect capacitive effects, the effective capacitance estimation including;
modeling a gate load at an output of the gate, including;
approximating an admittance of the gate load to a single capacitance model; and
approximating the admittance of the gate load to a Π
model; and
matching a gate response for the Π
model with the gate response for the single capacitance model to determine the effective capacitance.
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Abstract
An non-iterative approach for estimating interconnect capacitive effects. The non-iterative approach includes a method for estimating the interconnect capacitive effects. The method includes modeling the gate and estimating an effective capacitance for the interconnect capacitive effects. The effective capacitance estimation includes modeling the gate load at an output of the gate. The gate load modeling includes approximating an admittance of the gate load to a single capacitance model in addition to approximating the admittance of the gate load to a Π model. The gate load modeling also includes matching a gate response for the Π model with the gate response for the single capacitance model to determine the effective capacitance. Another aspect of the method for estimating the interconnect capacitive effects includes modeling the gate using an equivalent circuit, and modeling the load at an output of the gate. The gate load modeling includes determining Π model parameters that represent the load at the output of the gate. The parameters are associated with a response at the gate output. The effective capacitance estimation method further includes modeling a single capacitive load at the output of the gate. The single capacitive load modeling includes determining a gate delay for a threshold time at a threshold voltage. This delay determination accounts for the input voltage waveform, the voltage response at the gate output and the Π model parameters. The single capacitance modeling the capacitive load is determined using the threshold time. The effective capacitance is then derived taking into account the single capacitance, a total capacitance of the gate load, an intrinsic gate delay and a gate load delay for the total capacitance as a load.
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Citations
20 Claims
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1. A method for estimating interconnect capacitive effects, comprising:
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modeling a gate; and
estimating an effective capacitance that models the interconnect capacitive effects, the effective capacitance estimation including;
modeling a gate load at an output of the gate, including;
approximating an admittance of the gate load to a single capacitance model; and
approximating the admittance of the gate load to a Π
model; and
matching a gate response for the Π
model with the gate response for the single capacitance model to determine the effective capacitance.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for estimating interconnect capacitive effects on a response of a gate, comprising:
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modeling the gate;
determining Π
model parameters of a load at an output of the gate;
determining a gate delay for a threshold time (tthd) at a threshold voltage taking into account the Π
model parameters, the gate delay being associated with a voltage response at the gate output;
determining a capacitance of a single capacitance model of the load, the capacitance being dependent on the threshold time (tthd);
obtaining from a gate delay table a gate load delay for a total capacitance (Ctot) as the load and an intrinsic gate delay for a no load condition; and
determining an effective capacitance (Ceff) based on the capacitance of the single capacitance model, the intrinsic gate delay and the gate load delay.
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13. A method of estimating interconnect capacitive effects, comprising:
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modeling a gate using an equivalent circuit;
modeling a load at an output of the gate, including determining Π
model parameters, the Π
model representing the load at the gate output, the Π
model parameters being associated with a response at the gate output;
modeling the load using a single capacitance model, including;
determining a threshold time corresponding to a threshold voltage at the gate output; and
determining a capacitance of the single capacitance model using the threshold time;
obtaining an intrinsic gate delay;
obtaining a gate load delay for a total capacitance as a load; and
determining an effective capacitance taking into account the capacitance of the single capacitance model, total capacitance, intrinsic gate delay and gate load delay. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification