Interconnect capacitive effects estimation

• US 6,314,546 B1
• Filed: 03/26/1999
• Issued: 11/06/2001
• Est. Priority Date: 03/08/1999
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Muddu, Sudhakar
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/276,992
• Time in Patent Office: 956 Days
• Field of Search: 716/1, 716/2, 716/4, 716/5, 716/6
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An non-iterative approach for estimating interconnect capacitive effects. The non-iterative approach includes a method for estimating the interconnect capacitive effects. The method includes modeling the gate and estimating an effective capacitance for the interconnect capacitive effects. The effective capacitance estimation includes modeling the gate load at an output of the gate. The gate load modeling includes approximating an admittance of the gate load to a single capacitance model in addition to approximating the admittance of the gate load to a Π model. The gate load modeling also includes matching a gate response for the Π model with the gate response for the single capacitance model to determine the effective capacitance. Another aspect of the method for estimating the interconnect capacitive effects includes modeling the gate using an equivalent circuit, and modeling the load at an output of the gate. The gate load modeling includes determining Π model parameters that represent the load at the output of the gate. The parameters are associated with a response at the gate output. The effective capacitance estimation method further includes modeling a single capacitive load at the output of the gate. The single capacitive load modeling includes determining a gate delay for a threshold time at a threshold voltage. This delay determination accounts for the input voltage waveform, the voltage response at the gate output and the Π model parameters. The single capacitance modeling the capacitive load is determined using the threshold time. The effective capacitance is then derived taking into account the single capacitance, a total capacitance of the gate load, an intrinsic gate delay and a gate load delay for the total capacitance as a load.

Claims

1. A method for estimating interconnect capacitive effects, comprising:

modeling a gate; and

estimating an effective capacitance that models the interconnect capacitive effects, the effective capacitance estimation including;

modeling a gate load at an output of the gate, including;

approximating an admittance of the gate load to a single capacitance model; and

approximating the admittance of the gate load to a Π

model; and

matching a gate response for the Π

model with the gate response for the single capacitance model to determine the effective capacitance.

2. The method of claim 1, being implemented in a computer system.

3. A method of claim 1, wherein the effective capacitance has a value falling within a range extending between a total capacitance of the load and a capacitance of the single capacitance model, the capacitance being determined for a particular voltage waveform applied at an input of the gate and a threshold voltage at the gate output.

4. A method of claim 3, wherein the range is set by obtaining an intrinsic gate delay and a gate load delay, and wherein the intrinsic gate delay and the gate load delay are obtained using a table look-up.

5. A method of claim 3, wherein the voltage waveform is one of step and ramp voltage waveforms, and wherein based on the voltage waveform the single capacitance model includes one of a step input capacitance (C_step) and a ramp input capacitance (C_ramp).

6. The method of claim 1, wherein the gate is modeled using an equivalent circuit including a Thé

venin equivalent with an impedance driven by a voltage source.

7. The method of claim 6, wherein the impedance is determined such that non-linear characteristics of the gate are approximated as a piece-wise linear resistor.

8. The method of claim 1, wherein the gate is modeled using parameters including a slew rate and load capacitance.

9. The method of claim 1, wherein the Π

model is an RC Π

model including a resistor and two capacitors.

10. The method of claim 1, wherein the Π

model is an RLC model including a resistor, an inductor and two capacitors.

11. The method of claim 1, wherein the gate modeling is for solving a closed-form equation for a voltage response at a gate output.

12. A method for estimating interconnect capacitive effects on a response of a gate, comprising:

modeling the gate;

determining Π

model parameters of a load at an output of the gate;

determining a gate delay for a threshold time (t_thd) at a threshold voltage taking into account the Π

model parameters, the gate delay being associated with a voltage response at the gate output;

determining a capacitance of a single capacitance model of the load, the capacitance being dependent on the threshold time (t_thd);

obtaining from a gate delay table a gate load delay for a total capacitance (C_tot) as the load and an intrinsic gate delay for a no load condition; and

determining an effective capacitance (C_eff) based on the capacitance of the single capacitance model, the intrinsic gate delay and the gate load delay.

13. A method of estimating interconnect capacitive effects, comprising:

modeling a gate using an equivalent circuit;

modeling a load at an output of the gate, including determining Π

model parameters, the Π

model representing the load at the gate output, the Π

model parameters being associated with a response at the gate output;

modeling the load using a single capacitance model, including;

determining a threshold time corresponding to a threshold voltage at the gate output; and

determining a capacitance of the single capacitance model using the threshold time;

obtaining an intrinsic gate delay;

obtaining a gate load delay for a total capacitance as a load; and

determining an effective capacitance taking into account the capacitance of the single capacitance model, total capacitance, intrinsic gate delay and gate load delay.

14. The method of claim 13, being implemented in a computer system.

15. The method of claim 13, further comprising providing a voltage waveform at an input of the gate to produce a response at the gate output, and wherein the voltage waveform is one of step and ramp voltage waveforms.

16. The method of claim 13, wherein the equivalent circuit is a thé

venin equivalent that substitutes the gate with a voltage source and a series resistor.

17. The method of claim 13, wherein the load is an interconnect tree load having a total resistance and the total capacitance, and wherein the parameters are determined in accordance with one of two relationships, a first of the two relationships being a function of the total capacitance and total resistance when the Π

model is an open-ended Π

model, and a second of the two relationships being a function of the first three moments of an admittance of the load when the Π

model is an accurate Π

model, the Π

model approximating the load admittance.

18. The method of claim 13, wherein the intrinsic gate delay and gate load delay are predetermined for various load values and are obtained from a cell library.

19. The method of claim 18, wherein for each gate in the cell library at least two gate delay tables exist, one for a delay and one for a slew rate.

20. The method of claim 19, wherein the format of the gate delay tables is equivalent to empirical K-factor formulas for delay and slew rate.