System processing unit extended with programmable logic for plurality of functions

• US 6,314,551 B1
• Filed: 06/22/1998
• Issued: 11/06/2001
• Est. Priority Date: 06/22/1998
• Status: Expired due to Term

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: Morgan Stanley & Co Incorporated (Morgan Stanley)
• Inventors: Borland, David J.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Speight, Jibreel
• Application Number:
  US09/102,465
• Time in Patent Office: 1,233 Days
• Field of Search: 716/16, 716/17, 710/129, 701/36, 711/112, 712/37, 712/39, 326/37-39
• US Class Current: 716/117
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

An integrated circuit including a main system processing unit which can be extended using a plurality of programmable logic unit for a plurality of possible functions, and a system for programming same. The integrated circuit also includes a plurality of functional logic blocks, a plurality of input/output (I/O) pads, and programmable logic coupled to each of the plurality of functional logic blocks. The main system processing unit is operable to perform a first function. Each of the plurality of functional logic blocks is operable to perform a respective function. The programmable logic is operable to route data to and from various ones of the plurality of functional logic blocks. The programmable logic is programmable to configure operation of two or more of the plurality of functional logic blocks and is also programmable to create data paths between two or of the plurality of functional logic blocks to configure the integrated circuit for one of the plurality of functions. The plurality of I/O pads is coupled to the main system processing unit and the plurality of functional logic blocks. The I/O pads are operable to transfer data signals between the integrated circuit and an external device. The programmable logic may perform a function different from each of the plurality of functional logic blocks. The system for programming the integrated circuit includes a computer system, the integrated circuit, and a cable for coupling the two.

Claims

1. An integrated circuit configurable for a plurality of possible functions, the integrated circuit comprising:

a main system processing unit;

a plurality of functional logic blocks, wherein the plurality of functional logic blocks are coupled to the main system processing unit, wherein each of the plurality of functional logic blocks is operable to perform a respective function;

programmable logic coupled to each of the plurality of functional logic blocks, wherein the programmable logic is operable to route data to and from various ones of the plurality of functional logic blocks, wherein the programmable logic is programmable to configure operation of two or more of the plurality of functional logic blocks and is programmable to create data paths between two or more of the plurality of functional logic blocks to configure the integrated circuit for one of the plurality of possible functions, wherein the main system processing unit is operable to program the programmable logic, and wherein the programmable logic is further configurable to selectively disable one or more of the functional logic blocks; and

a plurality of input/output (I/O) pads, wherein the plurality of I/O pads are coupled to the main system processing unit and the plurality of functional logic blocks, wherein the plurality of I/O pads are operable to transfer data signals between the integrated circuit and an external device.

2. The integrated circuit of claim 1, wherein the programmable logic is further configurable to perform a function different from each of the plurality of functional logic blocks.

3. The integrated circuit of claim 1, wherein the programmable logic is non-volatile.

4. The integrated circuit of claim 1, further comprising:

a memory for storing program instructions executable by the main system processing unit;

wherein the main system processing unit is operable to program the programmable logic in response to execution of said program instructions.

5. The integrated circuit of claim 4, wherein the main system processing unit is monitoring the program instructions, wherein the main system processing unit is operable to program the programmable logic in response to said monitoring the program instructions.

6. The integrated circuit of claim 4, wherein the program instructions are downloadable from the external device.

7. The integrated circuit of claim 1, wherein said selectively disable one or more functional blocks is permanent, wherein permanent comprises the one or more functional blocks to be disabled being no longer functional for their respective original purpose.

8. The integrated circuit of claim 1, wherein the programmable logic is further coupled to the main system processing unit and the plurality of I/O pads, wherein the programmable logic is further operable to route data to and from the main system processing unit, wherein the programmable logic is further operable to route data to and from the plurality of I/O pads.

9. The integrated circuit of claim 8, wherein the plurality of functional logic blocks include a first group of functional logic blocks and a second group of functional logic blocks, wherein the second group of functional logic blocks are redundant ones of the first group of functional logic blocks, wherein the programmable logic is operable to route data to one of the first group of functional logic blocks and a respective one of the second group of functional logic blocks.

10. The integrated circuit of claim 9, wherein the programmable logic is further configurable to reroute data bound to and from one of said first group of functional logic blocks to a redundant one of said second group of functional logic blocks.

11. The integrated circuit of claim 1 is further operable to dynamically reconfigure the programmable logic.

12. The integrated circuit of claim 11, wherein the dynamic reconfiguration of the programmable logic is in response to a program instruction, wherein the program instruction is executable by the main system processing unit.

13. The integrated circuit of claim 1, wherein one of the plurality of possible functions comprises one or more of:

a filter function, a transformation function, a computation function, and a relational function.

14. A system for configuring an integrated circuit for one of a plurality of possible functions, the system comprising:

a computer system, wherein said computer system includes;

a system bus for transferring commands and data;

a processor coupled to said system bus, wherein said processor is operable to execute said commands and operate on said data;

a memory which is operable to store said commands and said data in a form accessible by said processor; and

an I/O port coupled to said system bus, wherein said I/O port is operable to conduct programming instructions and data in response to processor operation; and

the integrated circuit, wherein the integrated circuit is configurable for a plurality of possible functions, wherein said integrated circuit includes;

a main system processing unit;

a plurality of functional logic blocks, wherein the plurality of functional logic blocks are coupled to the main system processing unit, wherein each of the plurality of functional logic blocks is operable to perform a respective function;

programmable logic coupled to each of the plurality of functional logic blocks, wherein the programmable logic is operable to route data to and from various ones of the plurality of functional logic blocks, wherein the programmable logic is programmable to configure operation of two or more of the plurality of functional logic blocks and is programmable to create data paths between two or more of the plurality of functional logic blocks to configure the integrated circuit for one of the plurality of possible functions, wherein the main system processing unit is operable to program the programmable logic, and wherein the programmable logic is further configurable to selectively disable one or more of the functional logic blocks; and

a plurality of input/output (I/O) pads, wherein the plurality of I/O pads are coupled to the main system processing unit and the plurality of functional logic blocks, wherein the plurality of I/O pads are operable to transfer data signals between the integrated circuit and said I/O port of said computer system; and

wherein said processor is operable to execute an application which provides said programming instructions and data to said I/O port, wherein said programming instructions and data operate to configure said integrated circuit with one of said plurality of possible functions,

wherein said application configures said programmable logic on said integrated circuit through said I/O port, wherein said integrated circuit receives a configuration from said application through said I/O pads; and

a cable for operatively coupling said I/O port and said I/O pads.

15. The system of claim 14, wherein said I/O port includes a plurality of computer system I/O pins,

wherein said integrated circuit further includes:

a plurality of I/O pins operatively coupled to said plurality of I/O pads, wherein one or more of said I/O pacs is operable to accept I/O from one or more of said plurality of I/O pins,

wherein the cable couples said plurality of computer system I/O pins to said plurality of I/O pins.

16. The system of claim 15, wherein said cable includes electrical or optical couplings.