Chip scale package with heat spreader and method of manufacture

• US 6,314,639 B1
• Filed: 02/23/1998
• Issued: 11/13/2001
• Est. Priority Date: 02/23/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Corisis, David J.
• Primary Examiner(s): Arbes, Carl J.
• Assistant Examiner(s): SMITH, SEAN PRENTISS
• Application Number:
  US09/028,134
• Time in Patent Office: 1,359 Days
• Field of Search: 298/25, 298/27, 298/30, 298/31, 257/704, 257/707, 257/738, 257/778, 361/709, 361/719
• US Class Current: 29/827
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49568 specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: Y10T 29/49004 : including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor

Abstract

A dense semiconductor flip-chip device is provided with a heat sink/spreading/dissipating member which is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Dice are bonded to the paddles by e.g. conventional die attach methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.

Claims

1. A method for manufacturing a semiconductor device assembly, comprising:

providing a substrate having at least one circuit on a first side thereof;

providing a semiconductor die having an active surface having at least one bond pad thereon and having a second surface;

providing a metallic paddle frame having left and right rails, opposing cross members connected to said left and right rails, and a paddle sized to cover said second surface of said semiconductor die connected to said left and right rails and said opposing cross-members, said paddle suspended between said left and right rails and said opposing cross-members for receiving said second surface of said semiconductor die thereon;

providing at least one conductive bump on said at least one bond pad on said active surface of said semiconductor die for connection to said at least one circuit on a first side of said substrate, said at least one conductive bump on said at least one bond pad of said semiconductor die forming a portion of a conductive ball-grid-array connection to said at least one circuit on a first side of said substrate;

attaching the second surface of said semiconductor die to said paddle;

disconnecting said paddle having said semiconductor die attached thereto from said paddle frame; and

connecting said at least one conductive bump on said at least one bond pad of the active surface of said semiconductor die to said at least one circuit on a first side of said substrate forming a portion of a conductive ball-grid-array connection to said substrate, said paddle attached to said second surface of said semiconductor die providing a heat sink for said semiconductor die during the operation thereof.

2. The method of claim 1, further comprising:

testing said semiconductor die for satisfactory electrical properties while said paddle is connected to said metallic paddle frame.

3. The method of claim 1, wherein said substrate includes a circuit board having at least one circuit thereon.

4. The method of claim 1, wherein said semiconductor die is attached to said paddle by an electrically non-conductive material.

5. The method of claim 4, wherein said electrically non-conductive material includes a non-conductive adhesive material.

6. The method of claim 5, wherein said non-conductive adhesive material comprises a polymer.

7. The method of claim 5, wherein said non-conductive adhesive material comprises one of polyimide and epoxy.

8. The method of claim 5, wherein said non-conductive adhesive material comprises a polyimide tape.

9. The method of claim 5, wherein said non-conductive adhesive material comprises a polyimide tape having an adhesive coating on both sides thereof.

10. The method of claim 1, wherein said second surface of said semiconductor die is attached to said paddle by an electrically conductive material.

11. The method of claim 10, wherein said electrically conductive material comprises a eutectic material.

12. The method of claim 11, wherein said eutectic material comprises a gold-silicon eutectic layer.

13. The method of claim 2, wherein said substrate includes a substrate having a plurality of circuits formed thereon;

wherein said at least one conductive bump includes a plurality of conductive bumps on said plurality of bond pads on said active surface of said semiconductor die; and

wherein said method further comprises connecting a plurality of conductive bumps to said plurality of circuits.