Methods for fabricating a multiple modular assembly

• US 6,316,278 B1
• Filed: 03/16/1999
• Issued: 11/13/2001
• Est. Priority Date: 03/16/1999
• Status: Expired due to Term

• Current Assignee: RUIZHANG TECHNOLOGY LIMITED COMPANY
• Original Assignee: Alien Technology Corporation
• Inventors: Craig, Gordon S. W., Jacobsen, Jeffrey Jay, Gengel, Glenn Wilhelm
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, DUNG ANH
• Application Number:
  US09/270,159
• Time in Patent Office: 973 Days
• Field of Search: 438/106, 438/22, 438/23, 438/24, 438/30, 313/511, 250/208.1, 156/655.1
• US Class Current: 438/22
• CPC Class Codes: G02F 1/133305 Flexible substrates, e.g. plastics, organic film
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/7665 Means for transporting the components to be connected
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/95101 in a liquid medium
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/76 Apparatus for connecting with build-up interconnects
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15155 : the shape of the recess being other than a cuboid
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Methods and apparatus for fabricating a multiple display modular assembly. In one example of a method, a first flexible layer is coupled to a substrate, a second flexible layer is coupled to the first flexible layer, and a third flexible layer is coupled to the second flexible layer. Each of the flexible layers may be generated from a separate web-line process. In one example, one flexible layer may have a display plane with a driver backplane, a second flexible layer may have a fine interconnect, and a third flexible layer may have gross interconnect. The multiple flexible layer modular assembly may apply to either flexible or rigid displays.

Claims

1. A method for fabricating an assembly, said method comprising:

dispensing a slurry over a substrate, said slurry containing a plurality of shaped blocks which are deposited onto receptor regions of said substrate and which each contain at least one functional component;

coupling a first flexible layer to said substrate; and

coupling a second flexible layer to said first flexible layer.

2. The method as in claim 1, said method further comprising the step of coupling the second flexible layer to the first flexible layer through depositing a display medium onto the first flexible layer.

4. The method as in claim 1 or 3 further comprising coupling a third flexible layer to the second flexible layer.

5. The method as in claim 1 or 3 wherein a display backplane is coupled to the first flexible layer.

6. The method as in claim 1 or 3 wherein a fine interconnect is deposited onto the second flexible layer.

7. The method as in claim 1 or 3 wherein gross interconnect is deposited onto the third flexible layer.

8. The method as in claim 1 or 3 wherein said second flexible layer is coupled to said first flexible layer.

9. The method as in claim 1 or 3 wherein said substrate is flexible.

10. The method as in claim 1 or 3 wherein said substrate is rigid.

11. The method as in claim 1 or 3 further comprising:

depositing a first layer of interconnect onto said first flexible layer;

depositing a dielectric layer onto the first layer of interconnect; and

depositing a second layer of interconnect onto the first layer of interconnect.

12. The method as in claim 1 or 3 further comprising:

depositing a first layer of interconnect onto said second flexible layer;

depositing a dielectric layer onto the first layer of interconnect; and

depositing a second layer of interconnect onto the first layer of interconnect.

13. The method as in claim 1 or 3 further comprising:

depositing a first layer of interconnect onto a first surface of the first flexible layer;

depositing a second layer of interconnect onto a second surface of the first flexible layer.

14. The method as in claim 1 or 3 further comprising:

depositing a first layer of interconnect onto a first surface of the second flexible layer;

depositing a second layer of interconnect onto a second surface of the second flexible layer.

15. The method as in claim 4 further comprising:

depositing a first layer of interconnect onto a first surface of the third flexible layer;

depositing a second layer of interconnect onto a second surface of the third flexible layer.

16. The method as in claim 1 further comprising:

grasping at least one shaped block with a robotic arm and depositing at least one said shaped block onto said substrate.

17. The method as in claim 1 or 3 wherein each of said shaped blocks comprises a pixel electrode for an active matrix display panel.

18. The method as in claim 1 or 3 wherein each of said shaped blocks comprises a pixel electrode for a passive matrix display panel.

19. The method as in claim 1 or 3 wherein the first flexible layer comprises a material selected from polyether sulfone, polyethylene terephthalate, polycarbonate, polybutylene terephthalate, polyphenylene sulfide, polypropylene, polyester, aramid, polyamide-imide, polyimide, aromatic polyimides, polyetherimide, metallic materials, acrylonitrile butadiene styrene, polyvinyl chloride, polyethylene naphthate, polybutylene naphthalate, and polycycloolefins.

20. The method as in claim 1 or 3 wherein the second flexible layer comprises a material selected from the group of polyether sulfone, polyethylene terephthalate, polycarbonate, polybutylene terephthalate, polyphenylene sulfide, polypropylene, polyester, aramid, polyamide-imide, polyimide, aromatic polyimides, polyetherimide, metallic materials, acrylonitrile butadiene styrene, polyvinyl choloride, polyethylene naphthate, polybutylene naphthalate, and polycycloolefins.

21. The method as in claim 4 wherein the third flexible layer comprises a material selected from the group of polyether sulfone, polyethylene terephthalate, polycarbonate, polybutylene terephthalate, polyphenylene sulfide, polypropylene, polyester, aramid, polyamide-imide, polyamide, aromatic polyimides, polyetherimide, metallic materials, acrylonitrile butadiene styrene, polyvinyl choloride, polyethylene naphthate, polybutylene naphthalate, and polycycloolefins.

22. The method as in claim 1 or 3 wherein the first flexible layer comprises a polymer material.

23. The method as in claim 1 or 3 wherein the second flexible layer comprises a polymer material.

24. The method as in claim 4 wherein the third flexible layer comprises a polymer material.

25. The method as in claim 1 or 3 wherein the second flexible layer is coupled to the first flexible layer through a display medium.

26. The method as in claim 17 wherein the assembly has a display medium which is liquid crystal.

27. The method as in claim 17 wherein the assembly has a display medium which comprises organic light emitting diode.

3. A method for fabricating an assembly having a plurality of electrical blocks, said method comprising:

depositing a plurality of blocks onto a substrate, each of said plurality of blocks comprising at least one electrical component fabricated in a semiconductor material;

coupling a first flexible layer to said substrate; and

coupling a second flexible layer to said first flexible layer.