Method of manufacturing semiconductor devices separated from a wafer

• US 6,316,280 B1
• Filed: 03/17/1999
• Issued: 11/13/2001
• Est. Priority Date: 09/07/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Fujiwara, Masatoshi
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): NOVACEK, CHRISTY L
• Application Number:
  US09/271,257
• Time in Patent Office: 972 Days
• Field of Search: 438/22, 438/31, 438/33, 438/34, 438/39, 438/460, 438/462, 438/465, 438/942, 438/945
• US Class Current: 438/31
• CPC Class Codes: H01S 5/0201 Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
• CPC Class Codes: H01S 5/0202 Cleaving
• CPC Class Codes: H01S 5/0203 Etching
• CPC Class Codes: H01S 5/0205 during growth of the semiconductor body
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/945 Special, e.g. metal

Abstract

A semiconductor device with an improved speed response has a linear ridge pattern including an active layer, a cladding layer, a current blocking layer, and a contact layer on a semiconductor substrate. The insulating layer may be formed in a pattern having a high resistance to dry etching along a longitudinal side of the ridge pattern.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a plurality of linear ridge patterns, each linear ridge pattern having a stripe shape, in a semiconductor substrate, including forming each linear ridge pattern by successively depositing an active layer and a cladding layer on a surface of said semiconductor substrate, forming an initial ridge of said active layer and said cladding layer, forming a current blocking layer beside and contacting side surfaces of said active layer and said cladding layer of the initial ridge, and covering said cladding layer and said current blocking layer of the initial ridge with a contact layer;

filling spaces between said ridge patterns with an organic dielectric layer contacting said ridge patterns;

covering all of each of said ridge patterns and parts of said organic dielectric layer with an insulating layer having an etching protecting pattern extending along said ridge patterns for avoiding over-etching along said ridge patterns;

etching said organic dielectric layer, using said insulating layer as an etching mask, in an oxygen plasma, leaving said organic dielectric layer in the same form as said insulating layer;

removing said insulating layer;

forming respective surface electrodes on said ridge patterns and said organic dielectric layer and further forming counter electrodes corresponding to said surface electrodes on a side of said substrate opposite said active layer; and

cutting said substrate along lines parallel and perpendicular to said ridge patterns to isolate a region including one of said ridge patterns and one of said electrodes, at least one of the lines corresponding to a cleavage plane of said semiconductor substrate.

2. The method according to claim 1, wherein said insulating layer includes a basic insulating layer pattern (a) and an etching protecting pattern (b), and, when a point at which said basic insulating layer pattern (a) contacts a longitudinal side of a ridge pattern is defined as an ideal point, said etching protecting pattern (b) prevents over-etching from the ideal point during oxygen etching, and said etching protecting pattern (b) has a length of at least 17.5 to 45 μ

m from said ideal point.

3. The method according to claim 1, wherein said etching protecting pattern (b), including a portion above said ridge pattern, has a width between 50 and 100 μ

m.

4. The method according to claim 1, wherein said etching protecting pattern (b) is not contiguous with said ridge pattern on the cleavage surface of said semiconductor substrate.

5. The method according to claim 1, wherein said organic dielectric layer is polyimide.

6. The method according to claim 1, wherein said organic dielectric layer has a thickness of 5.0 to 8.0 μ

m and said insulating layer has a thickness of 500 to 4,000 Å

.