Method for fabricating a hybrid optical integrated circuit employing SOI optical waveguide

• US 6,316,281 B1
• Filed: 09/10/1999
• Issued: 11/13/2001
• Est. Priority Date: 09/12/1998
• Status: Expired due to Term

• Current Assignee: Uniloc 2017 LLC (SoftBank Group Corp.)
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Song, Min Kyu, Hwang, Nam, Joo, Gwan Chong, Lee, Sang Hwan
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MAI, ANH D
• Application Number:
  US09/393,279
• Time in Patent Office: 795 Days
• Field of Search: 438/29, 438/31, 438/39, 438/40, 438/42, 438/43, 385/4, 385/14, 385/15, 385/49
• US Class Current: 438/31
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: G02B 6/30 for use between fibre and thin-film device
• CPC Class Codes: G02B 6/42 Coupling light guides with opto-electronic elements
• CPC Class Codes: G02B 6/4201 Packages, e.g. shape, construction, internal or external details
• CPC Class Codes: G02B 6/4214 the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device G02B6/4246 takes precedence
• CPC Class Codes: G02B 6/4224 using visual alignment markings, e.g. index methods
• CPC Class Codes: G02B 6/423 using guiding surfaces for the alignment
• CPC Class Codes: G02B 6/4232 using the surface tension of fluid solder to align the elements, e.g. solder bump techniques flip-chip mounting techniques in assembly of semiconductor devices H01L24/81
• CPC Class Codes: G02B 6/4243 Mounting of the optical light guide into a groove mounting optical light guides into a groove in general G02B6/3636
• CPC Class Codes: H01L 31/02325 the optical elements not being integrated nor being directly associated with the device

Abstract

The present invention relates to an optical integrated circuit; and, more particularly, to a method for preparing an improved hybrid optical integrated circuit which is capable of accommodating optical waveguides, optical devices, such as light emitting devices and light receiving devices, and optical fibers in an effective manner. The present invention has the advantages of minimizing horizontal misalignment error between the SOI waveguide rib area, the V-groove etch window and the alignment marks, decreasing the manufacturing cost by passively aligning the waveguides, the optical devices and the optical fibers on a single substrate. Also, the present invention has an effect of reducing fresnel reflection loss by providing the LPCVD silicon nitride layer capable of being used as an anti-reflection coating layer at both ends of the waveguide.

Claims

1. A method for fabricating a hybrid optical integrated circuit, the method comprising the steps of:

a) providing a SOI wafer including a silicon substrate, a buried insulating layer and a single crystal silicon layer;

b) selectively etching the single crystal silicon layer, thereby forming a SOI slab;

c) forming a silicon nitride layer and an etching mask layer on the resulting structure, wherein the silicon nitride layer is formed by a low pressure chemical vapor deposition process;

d) selectively etching the etching mask layer and the silicon nitride layer to expose the single crystal silicon layer in the SOI slab except a rib area and simultaneously forming a V-groove etch window for aligning an optical fiber and marks for aligning an optical device, wherein the a rib region in the SOI slab is covered with the silicon nitride layer and the etching mask layer;

e) selectively etching the exposed single crystal silicon layer to form a SOI rib;

f) selectively etching the etching mask layer and the silicon nitride layer on the SOI rib;

g) forming a cladding layer for an optical waveguide on a surface of the SOI slab and the SOI rib;

h) anisotropically etching the silicon substrate exposed through the V-groove etch window to form an optical fiber guiding V-groove; and

i) selectively removing the etching mask layer positioned at both end facets of the SOI slab and exposing the silicon nitride layer.

2. The method in accordance with claim 1, wherein the method further comprises the step of forming a trench crossing the optical fiber guiding V-groove, being adjacent to the SOI slab.

3. The method in accordance with claim 1, wherein the step g) further comprises the step of forming a metal pad for electrically connecting the optical device to the SOI wafer and a metal pad for solder bumps.

4. The method in accordance with claim 3, wherein the method

further comprises the step of forming the solder bumps.

5. The method in accordance with claim 1, wherein the SOI slab is in a Y-branch type.

6. The method in accordance with claim 1, wherein the SOI rib is tapered.

7. The method in accordance with claim 1, wherein the silicon nitride layer is formed by a LPCVD (low pressure chemical vapor deposition) method and a thickness (t) of the silicon nitride layer is given by:

8. The method in accordance with claim 1, wherein the cladding layer is a silicon oxide layer which is formed by a thermal oxidation.

9. The method in accordance with claim 1, wherein a ratio of a height of the SOI rib to a thickness of the single crystal silicon layer and a ratio of the height of the SOI rib to a width of the SOI rib are controlled to transmit only one fundamental mode in a vertical and horizontal direction.

10. The method in accordance with claim 1, wherein the single crystal silicon layer has a <

100>

direction.

11. The method in accordance with claim 10, wherein the SOI rib and the V-groove etch window are aligned in the <

110>

direction so that the V-groove etch window is surrounded with a surface of (111) crystalline plane.