Passivation layer for packaged integrated circuits

• US 6,316,285 B1
• Filed: 09/08/1999
• Issued: 11/13/2001
• Est. Priority Date: 09/02/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jiang, Tongbi, Yin, Zhiping
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): JONES, JOSETTA I
• Application Number:
  US09/392,201
• Time in Patent Office: 797 Days
• Field of Search: 438/106, 438/127
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/12043 Photo diode
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Passivating layers methods for forming the same are provided for packaged integrated circuit devices. In particular, an integrated circuit die is mounted in a plastic leaded chip carrier, and a photosensitive material is then deposited over the surfaces to be passivated. Portions of the photosensitive material are then exposed to UV light, resulting in a crosslinked siloxane network. In this way, a low-temperature photodefinable passivation layer is provided for the package, with characteristics similar to conventional oxides. Advantageously, the photosensitive material can be patterned during the UV exposure, and unexposed portions selectively removed to leave the passivation layer only over desired portions of the package.

Claims

1. A process for forming a passivated integrated circuit device, comprising:

mounting a die onto a surface of a die carrier;

reacting an organosilane precursor to form a layer of photosensitive material onto surfaces of the die and the die carrier;

exposing a first portion of the photosensitive material to UV light while sheltering a second portion of the photosensitive material from the UV light; and

exposing the photosensitive material to halogen-based plasma to remove the second portion of the photosensitive material.

2. The process of claim 1, wherein the second portion of the photosensitive material covers a conductive contact of the die carrier prior to removing the second portion.

5. The process of claim 1, further comprising exposing the photosensitive material to oxygen.

6. The process of claim 1, wherein the organosilane precursor comprises methylsilane.

7. The process of claim 6, wherein reacting the organosilane comprises flowing between about 40 sccm and 150 sccm of methylsilane and between about 1,000 sccm and 3,000 sccm of helium.

8. The process of claim 1, wherein the die carrier comprises a plastic substrate.

9. The process of claim 8, wherein reacting the organosilane comprises maintaining a temperature below about 150°

C.

10. The process of claim 8, wherein the plastic substrate comprises a BT resin.

11. The process of claim 1, wherein the die carrier comprises a plastic ball grid array.

3. A method of packaging an integrated circuit die to form a surface mount device, comprising:

mounting the die onto a surface of a plastic die carrier; and

depositing a photodefinable layer on the die and the die carrier after mounting the die; and

converting the photodefinable layer to a passivation layer, said converting comprising exposing at least a first portion of the photodefinable layer to UV light in an oxygenated environment.

4. The method of claim 3 further comprising dry development of an unexposed second portion of the photodefinable layer using a chlorine-based plasma, after exposing the first portion to UV light.

12. The method of claim 3, wherein depositing and converting are each conducted at temperatures of less than about 300°

C.

13. The method of claim 12, wherein depositing the photodefinable layer comprises reacting methylsilane at between about 90°

C. and 140°

C.

14. The method of claim 3, wherein the die carrier comprises a plastic ball grid array.

15. The method of claim 3, wherein the die carrier comprises a stackable integrated circuit die package.

16. The method of claim 3, wherein the photodefinable layer comprises plasma polymerized methylsilane.

17. The method of claim 3, wherein the die carrier comprises a printed circuit.

18. The method of claim 3, wherein the die carrier comprises a substrate formed of BT resin.