Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant

• US 6,316,302 B1
• Filed: 06/26/2000
• Issued: 11/13/2001
• Est. Priority Date: 06/26/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheek, Jon D., Wristers, Derick J., Toprac, Anthony J.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LUU, CHUONG A
• Application Number:
  US09/604,051
• Time in Patent Office: 505 Days
• Field of Search: 438/301, 438/303, 438/305, 438/306, 438/307, 438/576, 438/289, 438/291, 438/494, 438/495, 438/592, 438/655, 438/682, 438/184, 438/185, 438/199, 257/336, 257/344
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n⁺ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p⁻ LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.

Claims

1. A method for forming an integrated circuit, comprising:

providing first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate;

implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor;

subsequent to said implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor, forming first and second pairs of sidewall spacers extending laterally from respective first and second opposed sidewall surfaces of the first and second gate conductors;

implanting the first type of dopant into source and drain regions of the first active area spaced from the first gate conductor by the first pair of sidewall spacers;

isotropically etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers; and

implanting a second type of dopant into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced lateral thickness.

2. The method of claim 1, wherein the first active area is laterally spaced from the second active area by an isolation structure.

3. The method of claim 1, further comprising, prior to said implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor, forming a first masking layer across the second gate conductor and the second active area.

4. The method of claim 3, wherein the first type of dopant is implanted into the first source and drain regions at a second concentration greater than the first concentration.

5. The method of claim 4, further comprising removing the first masking layer from the second gate conductor and the second active area prior to said forming first and second pairs of sidewall spacers.

6. The method of claim 5, further comprising forming a second masking layer across the second gate conductor, the second pair of sidewall spacers, and the second active area prior to said implanting the first type of dopant into the first source and drain regions.

7. The method of claim 6, wherein the first type of dopant comprises an n-type dopant species.

8. The method of claim 6, further comprising removing the second masking layer prior to said isotropically etching the first and second pairs of sidewall spacers.

9. The method of claim 8, further comprising forming a third masking layer across the first gate conductor, the first pair of sidewall spacers, and the first source and drain regions prior to said implanting a second type of dopant into regions of the second active area.

10. The method of claim 9, wherein the second type of dopant comprises a p-type dopant species.

11. The method of claim 9, further comprising removing the third masking layer, and forming third and fourth pairs of sidewall spacers laterally extending from the first and second pairs of sidewall spacers, respectively, subsequent to said implanting a second type of dopant into regions of the second active area.

12. The method of claim 11, further comprising forming a fourth masking layer across the first gate conductor, the first and third pairs of sidewall spacers, and the first active area.

13. The method of claim 12, further comprising implanting the second type of dopant into second source and drain regions of the second active area at a higher concentration than said implanting a second type of dopant into regions of the second active area, wherein the second source and drain regions are spaced from the second gate conductor by the second and fourth pairs of sidewall spacers.

14. A method for forming an integrated circuit, comprising:

forming a first pair of sidewall spacers on opposed sidewall surfaces of a first gate conductor and a second pair of sidewall spacers on opposed sidewall surfaces of a second gate conductor;

implanting a first type of dopant into first regions of a semiconductor substrate self-aligned to outer lateral edges of said first pair of sidewall spacers;

etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers;

implanting a second type of dopant into second regions of the semiconductor substrate self-aligned to outer lateral edges of the second pair of sidewall spacers having the reduced lateral thickness;

subsequent to said etching, forming a third pair of sidewall spacers laterally extending from said first pair of sidewall spacers and a fourth pair of sidewall spacers laterally extending from said second pair of sidewall spacers; and

implanting the second type of dopant into third regions of the semiconductor substrate self-aligned to outer lateral edges of the fourth pair of sidewall spacers.

15. The method as recited in claim 14, further comprising, prior to said forming a first pair of sidewall spacers, implanting the first type of dopant into fourth regions of the semiconductor substrate self-aligned to outer lateral edges of said first gate conductor.

16. The method as recited in claim 14, wherein the combined lateral thickness on each side of said second gate conductor of said second pair of sidewall spacers after said etching and said fourth pair of sidewall spacers is greater than said second pair of sidewall spacers before said etching.

17. The method as recited in claim 14, wherein said first and second sidewall spacers are formed from a single type of spacer material.

18. A method for forming an integrated circuit, comprising:

providing first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate;

forming first and second pairs of sidewall spacers extending laterally from respective first and second opposed sidewall surfaces of the first and second gate conductors, wherein said first and second sidewall spacers are formed from a single type of spacer material;

implanting a first type of dopant into source and drain regions of the first active area spaced from the first gate conductor by the first pair of sidewall spacers;

isotropically etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers; and

implanting a second type of dopant into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced lateral thickness.

19. The method as recited in claim 18, further comprising prior to said forming first and second pairs of sidewall spacers, implanting the first type of dopant into regions of the first active area self-aligned to first gate conductor.

20. The method as recited in claim 18, further comprising, subsequent to said implanting a second type of dopant:

forming third and fourth pairs of sidewall spacers laterally extending from said first and second pairs of sidewall spacers respectively; and

implanting the second type of dopant into source and drain regions of the second active area spaced from the second gate conductor by the combined lateral thickness of the second pair of sidewall spacers having the reduced lateral thickness and the fourth pair of sidewall spacers.

21. A method for forming an integrated circuit, comprising:

forming a first pair of sidewall spacers on opposed sidewall surfaces of a first gate conductor and a second pair of sidewall spacers on opposed sidewall surfaces of a second gate conductor;

forming first dopant regions self-aligned said first pair of sidewall spacers;

etching the second pair of sidewall spacers to reduce a lateral thickness of the second pair of sidewall spacers;

forming second dopant regions self-aligned to the second pair of sidewall spacers having the reduced lateral thickness;

subsequent to said etching, forming an additional pair of sidewall spacers laterally extending from said second pair of sidewall spacers; and

forming third dopant regions self-aligned to the additional pair of sidewall spacers.