Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
First Claim
1. A method for forming an integrated circuit, comprising:
- providing first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate;
implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor;
subsequent to said implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor, forming first and second pairs of sidewall spacers extending laterally from respective first and second opposed sidewall surfaces of the first and second gate conductors;
implanting the first type of dopant into source and drain regions of the first active area spaced from the first gate conductor by the first pair of sidewall spacers;
isotropically etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers; and
implanting a second type of dopant into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced lateral thickness.
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Abstract
A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
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Citations
21 Claims
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1. A method for forming an integrated circuit, comprising:
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providing first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate;
implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor;
subsequent to said implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor, forming first and second pairs of sidewall spacers extending laterally from respective first and second opposed sidewall surfaces of the first and second gate conductors;
implanting the first type of dopant into source and drain regions of the first active area spaced from the first gate conductor by the first pair of sidewall spacers;
isotropically etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers; and
implanting a second type of dopant into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced lateral thickness. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for forming an integrated circuit, comprising:
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forming a first pair of sidewall spacers on opposed sidewall surfaces of a first gate conductor and a second pair of sidewall spacers on opposed sidewall surfaces of a second gate conductor;
implanting a first type of dopant into first regions of a semiconductor substrate self-aligned to outer lateral edges of said first pair of sidewall spacers;
etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers;
implanting a second type of dopant into second regions of the semiconductor substrate self-aligned to outer lateral edges of the second pair of sidewall spacers having the reduced lateral thickness;
subsequent to said etching, forming a third pair of sidewall spacers laterally extending from said first pair of sidewall spacers and a fourth pair of sidewall spacers laterally extending from said second pair of sidewall spacers; and
implanting the second type of dopant into third regions of the semiconductor substrate self-aligned to outer lateral edges of the fourth pair of sidewall spacers. - View Dependent Claims (15, 16, 17)
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18. A method for forming an integrated circuit, comprising:
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providing first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate;
forming first and second pairs of sidewall spacers extending laterally from respective first and second opposed sidewall surfaces of the first and second gate conductors, wherein said first and second sidewall spacers are formed from a single type of spacer material;
implanting a first type of dopant into source and drain regions of the first active area spaced from the first gate conductor by the first pair of sidewall spacers;
isotropically etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers; and
implanting a second type of dopant into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced lateral thickness. - View Dependent Claims (19, 20)
forming third and fourth pairs of sidewall spacers laterally extending from said first and second pairs of sidewall spacers respectively; and
implanting the second type of dopant into source and drain regions of the second active area spaced from the second gate conductor by the combined lateral thickness of the second pair of sidewall spacers having the reduced lateral thickness and the fourth pair of sidewall spacers.
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21. A method for forming an integrated circuit, comprising:
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forming a first pair of sidewall spacers on opposed sidewall surfaces of a first gate conductor and a second pair of sidewall spacers on opposed sidewall surfaces of a second gate conductor;
forming first dopant regions self-aligned said first pair of sidewall spacers;
etching the second pair of sidewall spacers to reduce a lateral thickness of the second pair of sidewall spacers;
forming second dopant regions self-aligned to the second pair of sidewall spacers having the reduced lateral thickness;
subsequent to said etching, forming an additional pair of sidewall spacers laterally extending from said second pair of sidewall spacers; and
forming third dopant regions self-aligned to the additional pair of sidewall spacers.
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Specification