Method of forming a buried plate

• US 6,316,310 B1
• Filed: 11/24/1999
• Issued: 11/13/2001
• Est. Priority Date: 11/26/1998
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Siemens Microelectronics Limited (Siemens AG)
• Inventors: Wensley, Paul, Koffler, Guenther
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Kennedy, Jennifer M.
• Application Number:
  US09/449,362
• Time in Patent Office: 720 Days
• Field of Search: 438/392, 438/561, 438/249
• US Class Current: 438/249
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

Known methods for forming trench storage capacitors require the chemical vapour deposition (CVD) of an undoped silicon oxide layer in order to prevent auto doping of side wall of a semiconductor trench. This layer is deposited once an arsenic doped silicon oxide layer has been disposed and etched to an appropriate depth. Such a technique results in a complex and expensive process. It is therefore proposed to deposit (step 906) the undoped silicon oxide layer 108 in-situ immediately after the arsenic doped silicon oxide layer 106 has been deposited (step 904) and before etching takes place (step 910). It is thus possible to remove the CVD of the undoped silicon oxide, thereby simplifying the overall process and yielding a device having improved performance characteristics.

Claims

1. A method of forming a buried plate for a semiconductor trench, comprising the steps of:

depositing a first layer comprising a dopant;

depositing a second layer of undoped material on the first layer;

etching the first and second layers to a predetermined depth, such that after said etching an upper portion of said first layer relative to a bottom of said trench, is exposed;

with said upper portion exposed, annealing the first and second layers for out-diffusing the dopant onto the semiconductor trench; and

removing the first and second layers, wherein the first layer is not exposed to air before the second layer is deposited thereon.

2. A method as claimed in claim 1, wherein the first layer comprises arsenic doped glass.

3. A method as claimed in claim 1, wherein the second layer comprises undoped glass.

4. A method as claimed in claim 2, wherein the arsenic doped glass is deposited using Tetra Ethyl Arsenate (TEAS).

5. A method as claimed in claim 3, wherein the undoped glass is deposited using Tetra Ethyl Ortho Silicate (TEOS).

6. A method as claimed in 1, wherein after the etching step, an upper portion relative to the bottom of the trench, of the first layer is exposed.