Method for obtaining a thin film in particular semiconductor, comprising a protected ion zone and involving an ion implantation

• US 6,316,333 B1
• Filed: 07/14/1999
• Issued: 11/13/2001
• Est. Priority Date: 01/27/1997
• Status: Expired due to Term

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Aspar, Bernard, Bruel, Michel
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Schillinger, Laura M
• Application Number:
  US09/341,555
• Time in Patent Office: 853 Days
• Field of Search: 438/458, 438/586, 438/455, 438/483, 438/233, 438/234, 438/235, 438/225, 438/448, 438/449, 438/296, 438/297, 438/464, 438/585, 438/152, 438/153, 438/154, 438/301, 438/302, 438/303, 438/304
• US Class Current: 438/458
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

The invention relates to a process for obtaining a thin film from a substrate, the film being delimited in the substrate by ionic implantation and by heat treatment inducing a fracture line along which the film can be separated from the rest of the substrate. A particular area, for example composed of a gate oxide layer (15) and the channel area (19) of a MOS transistor (12) created in the substrate region (10) intended to form the tin film (20), this area may be protected by ionic implantation by masking using the transistor gate (16), which does not prevent the fracture from occurring provided that the width of the area does not exceed a limiting dimension determined for the material forming the substrate.

Claims

1. Process for obtaining a thin film starting from a semiconducting substrate, this thin film being composed of a region of the substrate adjacent to one of its faces and separated from the rest of the substrate, at least one transistor being created from the said region, the process comprising the following steps:

generation of the said transistor until at least two superposed areas making up the transistor are obtained, the upper area including the transistor gate acting as a means of masking the lower area by defining a width of the masked area in the substrate not exceeding a determined limiting dimension for the material of the said substrate,

ionic implantation of the substrate through the said surface of the substrate, capable of creating a layer of micro-cavities within the thickness of the substrate and at a depth close to the average ion penetration depth, delimiting the said region from the rest of the substrate except for an area corresponding to the masked area,

heat treatment at a sufficiently high temperature to make a fracture line along this layer of micro-cavities, this fracture line being either continuous if the width of the masked area is sufficiently small compared with the said limiting dimension, or discontinuous if the width of the masked area is not sufficiently small with respect to the said delimiting dimension,

cleavage of the thin film from the rest of the substrate, either by simple separation if the fracture line is continuous, or by the application of mechanical forces between the said region and the rest of the substrate if the fracture line is discontinuous.

2. Process according to claim 1, in which another step is included between the ionic implantation step and the heat treatment step, in which the substrate is rigidly bonded on the side of the said region that will form the thin film, with a stiffener.

3. Process according to claim 1, in which ionic implantation is done using hydrogen ions or rare gas ions.

4. Process according to claim 1, in which the said mechanical forces are bending and/or tension forces.

5. Process according to claim 1, in which the said mechanical forces are applied during the heat treatment step.

6. Process according to claim 1, in which the said mechanical forces are applied after the heat treatment step.

7. Process according to claim 1, in which the said masking means consist of a layer deposited on the said face of the substrate.

8. Process according to claim 1, in which the substrate is made of silicon, the transistor is a MOS transistor and the said lower area is the gate oxide layer and the channel area of this MOS transistor, the upper area comprises the polysilicon gate of the MOS transistor deposited on the gate oxide layer.

9. Process according to claim 1, in which the masking means also comprise a resin layer.

10. Process according to claim 1, in which the masking means also comprise spacers deposited on the flanks of the gate.