Area array type semiconductor package and fabrication method

• US 6,316,837 B1
• Filed: 11/30/1998
• Issued: 11/13/2001
• Est. Priority Date: 12/04/1997
• Status: Expired due to Fees

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Song, Chi-Jung
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/200,937
• Time in Patent Office: 1,079 Days
• Field of Search: 257/666, 257/676, 257/778, 257/737, 257/738
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32013 the layer connector being larger than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An area array type semiconductor package includes a plurality of conductive media, such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.

Claims

1. A chip package, comprising:

a lead frame including a plurality of leads and a die paddle;

an integrated chip having a plurality of bonding pads, wherein the chip is attached to the die paddle of the lead frame, and wherein the die paddle and adjoining portions of the leads are substantially co-planar;

a plurality of conductive media formed on the bonding pads of the chip; and

a molding resin that packages a predetermined area on the lead frame and the chip.

2. The package of claim 1, wherein certain portions of the leads of the lead frame are bent in an upward or downward direction.

3. The package of claim 1, wherein the chip is attached to a die paddle of the lead frame, and wherein an area of the die paddle is larger than an attachment surface area of the chip.

4. The package of claim 3, wherein a portion of said die paddle is bent or recessed.

5. The package of claim 1, wherein the chip is attached to a die paddle of the lead frame, and wherein an area of the die paddle is approximately the same size as an attachment area of the chip.

6. The package of claim 1, wherein a thermal-conducting adhesive attaches the chip to the lead frame.

7. The package of claim 1, wherein portions of the plurality of conductive media are exposed outside the resin.

8. The package of claim 1, wherein the bonding pads are formed on a first side of the chip, and the lead frame is attached to a second side of the chip.

9. A chip package, comprising:

a lead frame comprising a plurality of leads and a die paddle;

an integrated chip comprising a plurality of bonding pads, wherein the chip is attached to the die paddle of the lead frame, and wherein an area of the die paddle is approximately the same size as an attachment area of the chip;

a plurality of conductive media formed on the bonding pads of the chip; and

a molding resin that packages a predetermined area on the lead frame and the chip wherein a portion of the die paddle is exposed outside of the molding resin.

10. A chip package, comprising:

a lead frame comprising a plurality of leads and a die paddle;

an integrated chip comprising a plurality of bonding pads, wherein the chip is attached to the die paddle of the lead frame, and wherein a portion of said die paddle is bent or recessed;

a plurality of conductive media formed on the bonding pads of the chip; and

a molding resin that packages a predetermined area on the lead frame and the chip.

11. A chip package, comprising:

a lead frame having a plurality of leads and a die paddle;

an integrated chip having a plurality of bonding pads formed on a first surface of the chip, wherein a second surface of the chip is attached to the die paddle of the lead frame, the first and second surfaces being opposing surfaces;

a plurality of solder bumps or balls formed on the bonding pads of the first surface of the chip; and

a molding resin that packages a predetermined area on the lead frame and the chip.

12. The package of claim 11, wherein a portion of said die paddle is bent or recessed.

13. The package of claim 11, wherein an area of the die paddle is approximately the same size as an attachment area of the chip.

14. The package of claim 11, wherein the die paddle and adjoining portions of the leads are substantially co-planar.

15. The package of claim 11, wherein the die paddle has a hole, depression or dimple for receiving the chip.

16. The package of claim 11, wherein the lead frame further comprises a lead supporting member for supporting the plurality of leads.

17. The package of claim 11, wherein the lead frame comprises copper, a copper alloy or a tungsten alloy.

18. The package of claim 11, wherein the solder bumps or balls are substantially spherical.

19. The package of claim 11, wherein the solder bumps or balls are exposed outside the resin.

20. The package of claim 11, wherein an area of the die paddle is larger than an attachment surface area of the chip.

21. The package of claim 11, wherein the first surface of the integrated chip is exposed.