Predistortion circuit
First Claim
1. A predistortion circuit for compensating a non-linear characteristic of a following amplifier comprising:
- a line coupled between an input terminal and an output terminal for receiving an input signal;
an active element connected between said line and ground;
bias voltage supplying means for supplying a predetermined bias voltage to a control electrode of said active element;
phase compensation means connected in parallel to said active element; and
inverting means coupled to said control electrode for inverting a phase of said input signal and supplying the inverted input signal to said control electrode of said active element.
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Accused Products
Abstract
An input signal is phase-inverted to supply the inverted signal to a gate of an FET. When the gate-source voltage Vgs decreases, the differential resistance Rds of the FET increases. Moreover, the differential resistance Rds also increases when the drain-source voltage Vds increases. That is, if the magnitude of the input signal from the signal source (2) increases, the gate-source voltage Vgs decreases and the drain-source voltage Vds increases, so that the differential resistance Rds varies largely. This compensates the non-linearity of the following saturation amplifier. Phase compensation is also effected with a capacitor (stray capacitor) or an inductor connected in parallel to the FET in corporation of the phase inverter. The phase inverter may be structured using the stray capacitances of the FET.
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Citations
8 Claims
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1. A predistortion circuit for compensating a non-linear characteristic of a following amplifier comprising:
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a line coupled between an input terminal and an output terminal for receiving an input signal;
an active element connected between said line and ground;
bias voltage supplying means for supplying a predetermined bias voltage to a control electrode of said active element;
phase compensation means connected in parallel to said active element; and
inverting means coupled to said control electrode for inverting a phase of said input signal and supplying the inverted input signal to said control electrode of said active element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification