Predistortion circuit

• US 6,316,983 B1
• Filed: 12/01/2000
• Issued: 11/13/2001
• Est. Priority Date: 07/26/2000
• Status: Expired due to Fees

• Current Assignee: YRP Mobile Telecommunications Key Technology Research Laboratories Company Limited
• Original Assignee: YRP Mobile Telecommunications Key Technology Research Laboratories Company Limited
• Inventors: Kitamura, Keiichi
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/726,428
• Time in Patent Office: 347 Days
• Field of Search: 327/306, 327/307, 327/133, 327/317, 327/362, 330/149
• US Class Current: 327/317
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence

Abstract

An input signal is phase-inverted to supply the inverted signal to a gate of an FET. When the gate-source voltage Vgs decreases, the differential resistance Rds of the FET increases. Moreover, the differential resistance Rds also increases when the drain-source voltage Vds increases. That is, if the magnitude of the input signal from the signal source (2) increases, the gate-source voltage Vgs decreases and the drain-source voltage Vds increases, so that the differential resistance Rds varies largely. This compensates the non-linearity of the following saturation amplifier. Phase compensation is also effected with a capacitor (stray capacitor) or an inductor connected in parallel to the FET in corporation of the phase inverter. The phase inverter may be structured using the stray capacitances of the FET.

Claims

1. A predistortion circuit for compensating a non-linear characteristic of a following amplifier comprising:

a line coupled between an input terminal and an output terminal for receiving an input signal;

an active element connected between said line and ground;

bias voltage supplying means for supplying a predetermined bias voltage to a control electrode of said active element;

phase compensation means connected in parallel to said active element; and

inverting means coupled to said control electrode for inverting a phase of said input signal and supplying the inverted input signal to said control electrode of said active element.

2. A predistortion circuit as claimed in claim 1, wherein said phase compensation means comprises a capacitance.

3. A predistortion circuit as claimed in claim 1, wherein said active element comprises a stray capacitance between a first electrode of said active element connected to said line and a second electrode of said active element connected to the ground, and said phase compensation means compensates a phase of said input signal with said stray capacitance.

4. A predistortion circuit as claimed in claim 1, wherein said phase compensation means comprises an inductor.

5. A predistortion circuit as claimed in claim 3, wherein said phase compensation means further comprises an inductor.

6. A predistortion circuit as claimed in claim 1, wherein said inverting means further comprises gain controlling means for controlling a gain of said inverting means to control an amount of compensating the non-linear characteristic.

7. A predistortion circuit as claimed in claim 3, wherein said inverting means further comprises gain controlling means for controlling a gain of said inverting means to control an amount of compensating the non-linear characteristic.

8. A predistortion circuit as claimed in claim 1, wherein said active element comprises a stray capacitance between a first electrode of said active element connected to said line and said control gate of said active element, and said inverting means comprises a capacitor connected between said control gate and the ground, and an inductor connected in equivalently parallel to said capacitor to invert said phase of said input signal with said stray capacitance, said capacitor, and said inductor.