Differential amplifier and a method of compensation

• US 6,316,998 B1
• Filed: 11/12/1998
• Issued: 11/13/2001
• Est. Priority Date: 11/12/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Oikawa, Naoto
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, KHANH V
• Application Number:
  US09/189,865
• Time in Patent Office: 1,097 Days
• Field of Search: 330/253, 330/255, 330/257, 330/297
• US Class Current: 330/255
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 3/265 with field-effect transistors only

Abstract

In a differential amplifier that is formed by a first differential amplifier formed by a first FET (MP1), to which a first input is applied, and a second FET (MP2), to which a second input is applied, a second differential amplifier formed by a third FET (MP7), to which the first input is applied, and a fourth FET (MP8), to which the second input is applied, in which each load of the first differential amplifier and the second differential amplifier being formed by a current mirror circuit, the signal to be fed to a subsequent stage is extracted from the drain D of the first FET (MP1) or the second FET (MP2).

Claims

1. A fully differential amplifier having push-pull outputs and an input stage which comprises:

a first differential amplifier pair including a first FET to which a first input is applied and a second FET to which a second input is applied;

a second differential amplifier pair including a third FET, to which the first input is applied and a fourth FET, to which the second input is applied;

a first current mirror circuit including a fifth FET and a sixth FET each serving as loads of said first FET and said fourth FET, respectively; and

a second current mirror circuit including a seventh FET and an eighth FET each serving as loads of said second FET and said third FET, respectively,

wherein a first output of said input stage is connected to a first push-pull amplifier, and a second output of said input stage is connected to a second push-pull amplifier,

wherein said fully differential amplifier is configured such that the first output of said input stage is taken out from a drain of one of the FETs forming said first current mirror circuit and a gate and a drain of said one of the FETs forming said first current mirror circuit are not connected to each other, and simultaneously therewith, the second output of said input stage is taken out from a drain of one of the FETs forming said second current mirror circuit and a gate and a drain of said one of the FETs forming said second current mirror circuit are not connected to each other,

wherein a first phase compensation circuit is provided between said drain of said one of the FETs forming said first current mirror circuit and an output of said first push-pull amplifier, and a second phase compensation circuit is provided between said drain of said one of the FETs forming said second current mirror circuit and an output of said second push-pull amplifier, and

wherein, between said output of said first push-pull amplifier and said drain of said one of the FETs forming said first current mirror circuit, are provided;

a ninth FET, a gate of which is connected to said drain of said one of the FETs forming said first current mirror circuit, a drain of which is connected to said output of said first push-pull amplifier, and a source of which is connected to a first power source;

a tenth FET, a source of which is connected to a second power source and a drain of which is connected to the output of said first push-pull amplifier;

an eleventh FET, a gate and a drain of which are connected to each other and forming a third current mirror circuit with said tenth FET;

a twelfth FET, a source of which is connected to said first power source and a drain of which is connected to a drain of said eleventh FET so as to drive said eleventh FET;

a thirteenth FET, a gate and a drain of which are connected to a gate of said twelfth FET and a drain of which is connected to one end of a first constant current source, and forming a fourth current mirror circuit with said twelfth FET;

a fourteenth FET, a gate of which connected to said drain of said one of the FETs forming said first current mirror circuit, a source of which is connected to said first power source, and a drain of which is connected to said first constant current source, and

wherein, between said output of said second first push-pull amplifier and said drain of said one of the FETs forming said second current mirror circuit, are provided;

a fifteenth FET, a gate of which is connected to said drain of said one of the FETs forming said second current mirror circuit, a drain of which is connected to said output of said second push-pull amplifier, and a source of which is connected to the first power source;

a sixteenth FET, a source of which is connected to said second power source and a drain of which is connected to the output of said second push-pull amplifier;

a seventeenth FET, a gate and drain of which are connected to each other and forming a fifth current mirror circuit with said sixteenth FET;

an eighteenth FET, a source of which is connected to said first power source and a drain of which is connected to a drain of said seventeenth FET so as to drive said seventeenth FET;

a nineteenth FET, a gate and a drain of which are connected to a gate of said eighteenth FET and a drain of which is connected to one end of a second constant current source, and forming a sixth current mirror circuit with said eighteenth FET; and

a twentieth FET, a gate of which is connected to said drain of said one of the FETs forming said second current mirror circuit, a source of which is connected to said first power source, and a drain of which connected to said drain of said nineteenth FET.