Clock recovery using an injection tuned resonant circuit

• US 6,317,008 B1
• Filed: 01/26/1999
• Issued: 11/13/2001
• Est. Priority Date: 01/26/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Gabara, Thaddeus J.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Glenn, Kimberly E
• Application Number:
  US09/236,675
• Time in Patent Office: 1,022 Days
• Field of Search: 331/25, 331/117.R, 331/167, 331/117.FE, 331/45, 331/172, 331/132, 331/113.R, 455/260, 455/264
• US Class Current: 331/117.00R
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Abstract

A tuning signal is injected into an LC tank circuit oscillator, e.g., through an impedance (either reactive, inductive, capacitive and/or resistive) to tune the phase and/or frequency of the LC tank circuit oscillator. A negative resistance is included in parallel with the LC tank circuit oscillator to compensate for losses in the LC tank circuit, and a bias signal is provided to power the operation of the LC tank circuit. Multiple LC tank circuit oscillators may be used to provide stable multiplied or divided frequencies. In another embodiment, the nominal frequency of the LC tank circuit oscillator may be adjusted using a varactor or other voltage-controlled element in the LC tank circuit oscillator under the control of, e.g., the output of a separate PLL loop including another LC tank circuit oscillator. In one application, the injection tuned LC tank circuit forms a clock recovery cell using a clock signal embedded in a NRZ (Non Return to Zero) pseudo-random data stream. The slave oscillator in turn generates a recovered clock signal. In another application, a sub-harmonic clock signal in a 5.6 Gb/s NRZ (Non Return to Zero) 2⁷−1 pseudo-random data stream is used to injection lock a CMOS LC tank circuit to 2.8 GHz. The data stream is de-serialized into two 2.8 Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock.

Claims

1. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor;

a negative resistance in parallel with at least one of said inductor and said capacitor; and

an impedance in communication with said LC tank circuit, said impedance comprising a capacitance being adapted and arranged to allow injection of a data signal into said LC tank circuit;

wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal.

2. The clock recovery cell according to claim 1, wherein said LC tank circuit further comprises:

a bias signal to provide power to said LC tank circuit.

3. The clock recovery cell according to claim 1, wherein said impedance comprises:

a transistor.

4. The clock recovery cell according to claims 3, wherein:

said transistor is a bipolar transistor.

5. The clock recovery cell according to claim 3, wherein:

said transistor is a field effect transistor.

6. The clock recovery cell according to claim 1, wherein:

a representation of said data signal is injected into each of at least two nodes of said clock recovery cell.

7. The clock recovery cell according to claim 1, further comprising:

an inductive element coupled with said inductor adapted and arranged to inject said data signal from said inductive element into said inductor;

wherein said impedance is formed by an insulating material.

8. The clock recovery cell according to claim 1, further comprising:

a phase locked loop adapted to provide a frequency control signal; and

at least one component in said LC tank circuit being adjustable under a control of said frequency control signal.

9. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor, said LC tank circuit tuned to a data signal and adapted to output a recovered clock signal;

a negative resistance in parallel with at least one of said inductor and said capacitor; and

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow infection of said data signal into said LC tank circuit;

wherein a representation of said data signal is infected into each of at least two nodes of said clock recovery cell, each of said representations of said data signal is phase shifted from another of said representations of said data signal.

10. The clock recovery cell according to claim 9, wherein:

said phase shift is approximately 180 degrees.

11. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor, wherein said LC tank circuit is outside a loop of said phase locked loop;

a negative resistance in parallel with at least one of said inductor and said capacitor;

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of said data signal into said LC tank circuit;

said phase locked loop adapted to provide a frequency control signal; and

at least one component in said LC tank circuit being adjustable under a control of said frequency control signal.

12. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor;

a negative resistance in parallel with at least one of said inductor and said capacitor; and

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of said data signal into said LC tank circuit;

a phase locked loop adapted to provide a frequency control signal, wherein said phase locked loop comprises a second LC tank circuit; and

at least one component in said LC tank circuit being adjustable under a control of said frequency control signal.

13. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor;

a negative resistance in parallel with at least one of said inductor and said capacitor;

and

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit; and

a directional coupler between said data signal and said LC tank circuit to limit a signal flow back from said LC tank circuit;

wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal.

14. A method of recovering a clock signal from a data signal, comprising:

injecting a data signal corresponding to said clock signal into an oscillator circuit tuned to said data signal; and

outputting said clock signal from said oscillator circuit wherein said oscillator circuit is tuned to a frequency corresponding to a fraction of a data rate of said data signal.

15. The method of recovering a data clock signal from a data signal according to claim 14, wherein:

said oscillator circuit is an LC tank circuit oscillator.

16. The method of recovering a data clock signal from a data signal according to claim 14, further comprising:

injecting a phase-shifted representation of said data signal into said oscillator circuit.

17. The method of recovering a data clock signal from a data signal according to claim 16, wherein:

said phase-shifted representation of said data signal is shifted 180°

with respect to said data signal.

18. Apparatus for recovering a clock signal from a data signal, comprising:

means for injecting a signal corresponding to said data signal into an oscillator circuit;

means for tuning said oscillator circuit to said data signal;

means for outputting said clock signal from said oscillator circuit wherein said means for tuning tunes said oscillator circuit to a frequency corresponding to approximately a data rate of said data signal; and

means for injecting a phase-shifted representation of said data signal into said oscillator circuit.

19. The apparatus for recovering a data clock signal from a data signal according to claim 18, wherein:

said oscillator circuit is an LC tank circuit oscillator.

20. An apparatus for recovering a data clock signal from a data signal according comprising:

means for injecting a signal corresponding to said data signal into an oscillator circuit;

means for tuning said oscillator circuit to said data signal, wherein said means for tuning tunes said oscillator circuit to a frequency corresponding to a fraction of a data rate of said data signal; and

means for outputting said clock signal from said oscillator circuit wherein said means for tuning tunes said oscillator circuit to a frequency corresponding to approximately a data rate of said data signal.

21. The apparatus for recovering a data clock signal from a data signal according to claim 20, wherein:

said fraction is approximately ½

.

22. An apparatus for recovering a data clock signal from a data signal comprising:

means for injecting a signal corresponding to said data signal into an oscillator circuit;

means for tuning said oscillator circuit to said data signal;

means for outputting said clock signal from said oscillator circuit wherein said means for tuning tunes said oscillator circuit to a frequency corresponding to approximately a data rate of said data signal; and

means for infecting a phase-shifted representation of said data signal into said oscillator circuit, wherein said phase-shifted representation of said data signal is shifted 180°

with respect to said data signal.

23. A data communication device, comprising:

a modem; and

a tuned oscillator, said tuned oscillator comprising;

an LC tank circuit comprising an inductor and a capacitor, and

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal and adapted to output a recovered clock signal;

wherein said tuned oscillator is tuned to a frequency corresponding to approximately a data rate of said data signal.

24. A clock recovery cell, comprising:

an LC tank circuit outside a loop of a phase locked loop comprising an inductor and a capacitor;

said phase locked loop adapted to provide a frequency control signal;

at least on component in said LC tank circuit being adjustable under a control of said frequency control signal;

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit; and

wherein said LC tank circuit is adapted to be tuned to a frequency corresponding to approximately a data rate of said data signal and is adapted to output a recovered clock signal.

25. A method of recovering a clock signal from a data signal, comprising:

injecting a data signal corresponding to said clock signal into an oscillator circuit;

tuning said oscillator circuit to said data signal; and

outputting said clock signal from said oscillator circuit wherein said oscillator circuit is tuned to a frequency corresponding to approximately ½

of a data rate of said data signal.

26. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor;

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit, wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal; and

a first flip/flop clocked by a recovered clock signal output from said LC tank circuit.

27. The clock recovery cell according to claim 26, wherein:

said first flip/flop receives a signal containing digital data information, and outputs a recovered data signal.

28. The clock recovery cell according to claim 27, wherein:

said output recovered data signal contains approximately half of said digital data information contained in said received signal.

29. The clock recovery cell according to claim 27, further comprising:

a second flip/flop clocked by an inverse of said frequency signal;

said first flip/flop receiving said data signal, and outputting a first recovered data signal containing a first portion of digital data information contained in said data signal; and

said second flip/flop receiving said data signal, and outputting a second recovered data signal containing a second portion of digital data information contained in said data signal.

30. The clock recovery cell according to claim 29, wherein:

said first portion of said digital data information is one half of digital data information contained in said data signal; and

said second portion of said digital data information is a second half of digital data information contained in said data signal.

31. The clock recovery cell according to claim 30, wherein:

said one half of said digital data information and said second half of said digital data information are interleaved.

32. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor;

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal; and

a directional coupler between said data signal and said LC tank circuit to limit a signal flow back from said LC tank circuit.

33. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor;

an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal; and

a representation of said data signal phase shifted from another of said representations of said data signal injected into each of at least two nodes of said clock recovery cell.

34. The clock recovery cell according to claim 33, wherein:

said phase shift is approximately 180 degrees.

35. A clock recovery cell, comprising:

an LC tank circuit comprising an inductor and a capacitor; and

an impedance connected to a node between said inductor and said capacitor, said impedance adapted and arranged to allow injection of a data signal into said LC tank circuit;

wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal.