DC offset correction adaptable to multiple requirements

• US 6,317,064 B1
• Filed: 02/29/2000
• Issued: 11/13/2001
• Est. Priority Date: 02/29/2000
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Salvi, Raul, Ferrer, Enrique, Goatley, James C., Tilley, Keith A.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US09/515,834
• Time in Patent Office: 623 Days
• Field of Search: 341/118, 455/234.2
• US Class Current: 341/118
• CPC Class Codes: H03F 1/304 and using digital means
• CPC Class Codes: H03F 3/45973 by using a feedback circuit
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295

Abstract

A DC offset correction method and apparatus. Several DC offset correction schemes including a digital binary search scheme (100), a digital slow averaging scheme (200) and an analog integration (50) scheme are provided. A controller (160) selects one or more of the correction schemes in accordance with the desired characteristics provided by each scheme.

Claims

1. A method for correcting a DC offset in an electronic circuit, comprising:

providing a first DC offset correction arrangement selectively coupled to the electronic circuit;

providing a second DC offset correction arrangement selectively coupled to the electronic circuit; and

selecting one of the first and second DC offset correction arrangements for correcting DC offset in the electronic circuit.

2. A method in accordance with claim 1, wherein the first DC offset correction arrangement comprises a digital binary search DC offset correction circuit.

3. A method in accordance with claim 1, wherein the second DC offset correction arrangement comprises a digital slow averaging DC offset correction circuit.

4. A method in accordance with claim 1, wherein the second DC offset correction arrangement comprises an analog integration DC offset correction circuit.

5. A method in accordance with claim 1, further comprising providing a third DC offset correction arrangement selectively coupled to the electronic circuit;

and wherein the selecting comprises selecting one of the first, second and third DC offset correction arrangements for correcting DC offset in the electronic circuit.

6. A method in accordance with claim 5, wherein the first DC offset correction arrangement comprises a digital binary search DC offset correction circuit, the second DC offset correction arrangement comprises a digital slow averaging DC offset correction circuit, and the third DC offset correction arrangement comprises an analog integration DC offset correction circuit.

7. A method in accordance with claim 2, wherein the digital binary search DC offset correction circuit comprises an enhanced digital binary search DC offset correction circuit.

8. A method in accordance with claim 6, carried out in one of a radio transmitter and a radio receiver.

9. A method in accordance with claim 1, wherein the selecting comprises first selecting the first DC offset correction arrangement and next selecting the second DC offset correction arrangement, wherein the first DC offset correction arrangement has a fast DC offset correction characteristic and wherein the second DC offset correction arrangement has a slow continuous DC offset correction characteristic.

10. A DC offset correction circuit, comprising:

a signal path, the signal path having a baseband filter, an input and an output;

a first DC offset correction feedback circuit selectively coupled to the signal path and operating in a first mode, which receives the signal path output and applies a DC offset correction voltage to the input of the signal path;

a second DC offset correction feedback circuit selectively coupled to the signal path and operating in a second mode, which receives the signal path output and applies a DC offset correction voltage to the input of the signal path; and

a controller which selects one of the first and the second DC offset correction feedback circuits for coupling to the signal path.

11. A circuit in accordance with claim 10, wherein the first DC offset correction feedback circuit comprises a digital binary search DC offset correction.

12. A circuit in accordance with claim 10, wherein the second DC offset correction feedback circuit comprises a digital slow averaging DC offset correction.

13. A circuit in accordance with claim 10, wherein the second DC offset correction feedback circuit comprises an analog integration DC offset correction circuit.

14. A circuit in accordance with claim 10, further comprising a third DC offset correction feedback circuit selectively coupled to the signal path and operating in a third mode, which receives the signal path output and applies a selected DC offset correction voltage to the input of the signal path;

and wherein the controller selects one of the first, second and third DC offset correction feedback circuits for coupling to the signal path.

15. A circuit in accordance with claim 14, wherein the first DC offset correction circuit comprises a digital binary search DC offset correction circuit, the second DC offset correction feedback circuit comprises a digital slow averaging DC offset correction circuit, and the third DC offset correction feedback circuit comprises an analog integration DC offset correction circuit.

16. A circuit in accordance with claim 13, wherein the analog integration DC offset correction circuit further comprises a resistor and a capacitor which determine an integration time constant.

17. A circuit in accordance with claim 16, wherein the controller further selects from among a plurality of resistor and capacitor combinations to establish one of a plurality of integration time constants.

18. A circuit in accordance with claim 10, wherein the controller first selects a DC offset feedback circuit having a fast correction characteristic and subsequently selects a DC offset feedback circuit having a continuous slow correction characteristic.

19. A circuit in accordance with claim 10, wherein the first and second DC offset feedback circuits are integrated into an integrated circuit.

20. A communication device, comprising:

a DC offset correction path, comprising;

a signal path, the signal path having a baseband filter, an input and an output;

a first DC offset correction feedback circuit selectively coupled to the signal path and operating in a first mode, which receives the signal path output and applies a DC offset correction voltage to the input of the signal path;

a second DC offset correction feedback circuit selectively coupled to the signal path and operating in a second mode, which receives the signal path output and applies a DC offset correction voltage to the input of the signal path; and

a controller which selects one of the first and the second DC offset correction feedback circuits for coupling to the signal path.