Vertical bipolar read access for low voltage memory cell

• US 6,317,357 B1
• Filed: 05/08/1999
• Issued: 11/13/2001
• Est. Priority Date: 02/24/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/328,074
• Time in Patent Office: 920 Days
• Field of Search: 365/149, 365/177, 365/225.6, 257/70, 257/302, 257/305, 438/202, 438/234
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A memory device is described which has an n-channel FET access transistor coupled between a memory cell and a data communication line. An NPN bipolar access transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar access transistor is described as coupled to a body of the n-channel access transistor to control threshold voltage variations of the n-channel FET access transistor. During operation the n-channel FET access transistor is used for writing data to a memory cell, while the NPN bipolar access transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.

Claims

1. A processing system comprising:

a processor; and

a memory device coupled to the processor, the memory device receives control signals from the microprocessor and comprises;

an n-channel FET access transistor coupled between a memory cell and a data communication line, and

an NPN bipolar access transistor coupled between the memory cell and the data communication line, such that the n-channel access transistor and the NPN bipolar access transistor are connected in parallel, a base connection of the NPN bipolar transistor is coupled to a body of the n-channel access transistor, wherein the FET access transistor writes the information from the external microprocessor, and wherein the NPN bipolar access transistor reads the information from the external microprocessor in conjunction with a current sense amplifier.

2. The processor system of claim 1 wherein the n-channel transistor and the NPN bipolar access transistor are fabricated as a single unit.

3. The processor system of claim 1 wherein the memory device is fabricated in a low voltage memory device receiving a supply voltage which is less than three volts.

4. The processor system of claim 1 wherein the memory device is a dynamic random access memory (DRAM).

5. A single transistor unit having an n-channel field effect transistor (FET) and an NPN bipolar transistor, the single transistor unit comprising:

a first n-type semiconductor layer which forms both an emitter of the n-channel FET and a collector of the NPN bipolar transistor,

a p-type semiconductor layer located above the first n-type semiconductor layer which forms a body of the n-channel FET and a base of the NPN bipolar transistor;

a second n-type semiconductor layer located above the p-type semiconductor layer which forms a drain of the n-channel FET and a collector of the NPN bipolar transistor;

a semiconductor region located laterally adjacent to the p-type semiconductor layer, the semiconductor region is laterally spaced from the p-type semiconductor layer by an insulator such that the semiconductor region forms a gate of the n-channel FET.

6. The single transistor unit of claim 5 wherein the p-type semiconductor layer has a vertical doping profile such that a top region of the p-type semiconductor layer is less heavily p-doped than bottom region of the p-type semiconductor layer.

7. The single transistor unit of claim 5 wherein the first and second n-type semiconductor layers have a p-plus doping.

8. The single transistor unit of claim 5 wherein the semiconductor region comprises polysilicon.

9. The single transistor unit of claim 5 wherein the first n-type semiconductor layer is formed on an insulator base.

10. The single transistor unit of claim 9 wherein the insulator base is oxide.

11. The single transistor unit of claim 5 wherein the first n-type semiconductor layer is formed on a p-type substrate.

12. The single transistor unit of claim 5 further comprising a polysilicon gate contact located laterally adjacent to the p-type semiconductor layer.

13. A single memory cell access transistor unit having an n-channel field effect transistor (FET) and an NPN bipolar transistor, the single transistor unit comprising:

a first n-type semiconductor region which forms both an emitter of the n-channel FET and a collector of the NPN bipolar transistor,

a p-type semiconductor region located above the first n-type semiconductor region which forms a body of the n-channel FET and a base of the NPN bipolar transistor;

a second n-type semiconductor region located above the p-type semiconductor region which forms a drain of the n-channel FET and a collector of the NPN bipolar transistor;

a semiconductor region located laterally adjacent to the p-type semiconductor region, the semiconductor region is laterally spaced from the p-type semiconductor region by an insulator such that the semiconductor region forms a gate of the n-channel FET.

14. The single memory cell access transistor unit of claim 13 wherein a memory cell coupled to the second n-type semiconductor region is written by coupling a low voltage to the p-type semiconductor region and a high voltage is coupled to the semiconductor region.

15. The single memory cell access transistor unit of claim 14 wherein the low voltage is approximately 0.7 volts and the high voltage is approximately 3.0 volts.

16. The single memory cell access transistor unit of claim 13 wherein a memory cell coupled to the second n-type semiconductor region is read by coupling a high voltage to the p-type semiconductor region and a low voltage is coupled to the semiconductor region.

17. The single memory cell access transistor unit of claim 16 wherein the high voltage is approximately 1.6 volts and the low voltage is approximately zero volts.