Multi-state memory

• US 6,317,363 B1
• Filed: 10/13/2000
• Issued: 11/13/2001
• Est. Priority Date: 01/14/1992
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Fong, Yupin Kawing, Guterman, Daniel C.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/687,986
• Time in Patent Office: 396 Days
• Field of Search: 365/185.01, 365/185.23, 365/185.03, 365/185.18, 365/185.2
• US Class Current: 365/185.23
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Claims

1. A multi-state memory comprising:

a plurality of EEPROM memory cells, each for storing one of a plurality of multi-states, organized into a plurality of sectors;

one or more tracking cells for each of said multi-states, associated with each of said plurality of sectors;

read circuitry for reading raw data associated with the programmed state of said tracking cells;

converter circuitry for converting said raw data to digital form; and

a memory controller for establishing desired read points for each of a plurality of physical states, based upon said raw data converted to digital form read from each said tracking cell.

2. A multi-state memory comprising:

a plurality of EEPROM memory cells, each for storing one of a plurality of multi-states, organized into a plurality of sectors;

one or more tracking cells for each of said multi-states, associated with each of said plurality of sectors;

read circuitry for reading raw data associated with the programmed state of said tracking cells;

converter circuitry for converting said raw data to digital form; and

a memory controller for establishing desired read points for each of a plurality of physical states, based upon said raw data converted to digital form read from each said tracking cell.