Dynamic random access memory

• US 6,317,366 B1
• Filed: 08/01/2000
• Issued: 11/13/2001
• Est. Priority Date: 12/26/1990
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okamura, Junichi, Furuyama, Tohru
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/630,585
• Time in Patent Office: 469 Days
• Field of Search: 365/230.06, 365/226, 365/149, 365/230.08, 365/189.09, 365/201, 365/189.08
• US Class Current: 365/189.08
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device includes a memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the memory cell, a charge pump circuit generating an internal power supply voltage which is boosted up from a power supply voltage, and outputting the internal power supply voltage, and a decoder circuit which receives address signals and has a P-channel MOS transistor for receiving the internal power supply voltage, the decoder circuit generating a word line selecting signal. Also, the semiconductor memory device includes a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a first MOS transistor and a second MOS transistor, the first MOS transistor having a first current path, a first end of the first current path being connected to a first node having the internal power supply voltage, a second end of the first current path being connected to the word line and a gate which is controlled in accordance with the word line selecting signal, the second MOS transistor having a second current path, a first end of the second current path being connected to the first MOS transistor, a second end of the second current path being connected to a predetermined potential lower than the internal power supply voltage, wherein the charge pump circuit outputs the internal power supply voltage for a first period in which at least the P-channel MOS transistor is in an ON state and a second period in which at least the first MOS transistor is in an ON state.

Claims

1. A semiconductor memory device, comprising:

a memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor;

a word line connected to a gate of the transfer N-channel MOS transistor of said memory cell;

a charge pump circuit generating an internal power supply voltage which is boosted up from a power supply voltage, and outputting the internal power supply voltage;

a decoder circuit which receives address signals and has a P-channel MOS transistor for receiving the internal power supply voltage, the decoder circuit generating a word line selecting signal; and

a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, said word line driving circuit being provided in correspondence with said word line and having a first MOS transistor and a second MOS transistor, said first MOS transistor having a first current path, a first end of the first current path being connected to a first node having the internal power supply voltage, a second end of the first current path being connected to said word line and a gate which is controlled in accordance with the word line selecting signal, said second MOS transistor having a second current path, a first end of the second current path being connected to said first MOS transistor, a second end of the second current path being connected to a predetermined potential lower than the internal power supply voltage, wherein said charge pump circuit outputs the internal power supply voltage for a first period in which at least said P-channel MOS transistor is in an ON state and a second period in which at least said first MOS transistor is in an ON state.

2. The device according to claim 1, wherein said charge pump circuit includes,

a clock signal generating circuit for generating a first clock signal and a second clock signal,

a first charge pump circuit which receives the first clock signal for performing a charge pump and supplying a charge pump output to a raised voltage output node, and

a second charge pump circuit which receives the second clock signal for performing a charge pump and supplying a charge pump output to the raised voltage output node.

3. The device according to claim 1, wherein the word line selecting signal is the steady-level voltage when the word line is not selected and the predetermined potential when the word line is selected, and said word line driving circuit charges the word line to the steady-level voltage via said second P-channel MOS transistor when the word line selecting signal is the predetermined potential and discharging the word line to the predetermined potential via said first N-channel MOS transistor when the selecting signal is the steady-level voltage.

4. The device according to claim 1, wherein said decoder circuit further includes a second N-channel MOS transistor, a third N-channel MOS transistor and a fourth N-channel MOS transistor connected in series between the first node and the ground terminal, said decoder circuit providing the word line selecting signal at a connection node between said first P-channel MOS transistor and said second N-channel MOS transistor.

5. The device according to claim 1, further comprising:

terminals for receiving external address signals;

address amplifying circuits coupled to said terminals, for generating first internal address signals for selecting a first number of said word lines in a normal operation mode in response to the external address signals; and

a control circuit for generating second internal address signals for selecting a second number of said word lines in a voltage stress test mode in response to a voltage stress test control signal, the second number being greater than the first number.

6. The device according to claim 5, wherein the first MOS transistor is a P-channel type MOS transistor and the second MOS transistor is an N-channel type MOS transistor.

7. The device according to claim 1, further comprising a third MOS transistor including,

a third current path having a first end connected to the gate of the first MOS transistor and a second end connected to the predetermined potential;

and

a gate which is controlled in accordance with a voltage stress test control signal for selecting a first number of said word lines in a voltage stress test mode, wherein the first number is greater than a second number of said word lines selected in a normal operation mode.

8. The device according to claim 7, wherein the first MOS transistor is a P-channel type MOS transistor and the second MOS transistor is an N-channel type MOS transistor.