Reference signal generation for magnetic random access memory devices

• US 6,317,376 B1
• Filed: 06/20/2000
• Issued: 11/13/2001
• Est. Priority Date: 06/20/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Eldredge, Kenneth J., Tran, Lung T.
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/598,671
• Time in Patent Office: 511 Days
• Field of Search: 365/210, 365/158, 365/209, 365/207, 365/171, 365/173
• US Class Current: 365/210.12
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.

Claims

1. A memory device comprising:

a block of memory cells;

a first storage device for storing a logic ‘

1’

;

a second storage device for storing a logic ‘

0’

;

a sense amplifier; and

a circuit for generating a reference signal for the sense amplifier, the circuit generating the reference signal by combining outputs of the first and second storage devices.

2. The device of claim 1, wherein the first storage device includes a first group of reference cells for the memory cells in the block;

wherein the second storage device includes a second group of reference cells for the memory cell block; and

wherein the circuit generates the reference signal by combining the outputs from the first and second reference cell groups;

the first and second groups being local to the block of memory cells.

3. The device of claim 2, wherein the first group includes a first column of first reference cells and the second group includes a second column of second reference cells;

wherein each memory cell in the array is crossed by a word line, each word line also crossing a first reference cell in the first reference cell group and a second reference cell in the second reference cell column;

whereby selecting a word line results in a corresponding pair of first and second reference cells being selected, outputs of the selected reference cell pair being combined by the circuit to generate the reference signal.

4. The device of claim 3, wherein a first bit line crosses the first reference cells in the first column;

wherein a second bit line crosses the second reference cells in the second column; and

wherein the circuit includes a half gain amplifier having inputs coupled to the first and second bit lines.

5. The device of claim 2, wherein the first group includes a first reference cell for storing a logic ‘

1’ and

the second group includes a second reference cell for storing a logic ‘

0’

;

wherein the first and second reference cells are crossed by a trace; and

wherein the circuit includes an amplifier having an input coupled to the trace.

6. The device of claim 5, further comprising an additional first reference cell for storing a logic ‘

1’

, an additional second reference cell for storing a logic ‘

0’

, and an additional trace crossing the additional reference cells; and

wherein the additional trace is also coupled to the amplifier input.

7. The device of claim 2, further comprising an additional first reference cell group, an additional second reference cell group, an additional circuit and an additional sense amplifier for each additional block of memory cells in the array, wherein each additional first reference cell group includes first reference cells for storing a logic ‘

1’

, each additional second reference cell group includes second reference cells for storing a logic ‘

0’

, and each additional circuit generates a reference signal for a corresponding sense amplifier by combining outputs of corresponding first and second reference cell groups; and

wherein each additional group of reference cells is local to its corresponding memory cell block.

8. The device of claim 1, further comprising a third storage device;

and wherein the circuit includes first, second and third switches and control logic for controlling the switches, the control logic causing the first switch to connect a selected memory cell to the third storage device during a first time interval, the control logic causing the second and third switches to connect the first and second storage devices to the selected memory cell during a second time interval, the control logic causing the second switch to connect the selected memory cell to the first storage device during a third time interval, the control logic causing the third switch to equalize signals stored in the first and second storage devices, the equalized signal being the reference signal.

9. The device of claim 1, further comprising a third storage device for storing a logic value of a selected memory cell in the block;

and wherein the circuit includes first, second, third and fourth switches and control logic for controlling the switches, the control logic causing the first switch to connect the selected memory cell to the third storage device during a first time interval, the control logic causing the second switch to connect the first storage device to the selected memory cell during a second time interval, the control logic causing the third switch to connect the selected memory cell to the second storage device during a third time interval, and the control logic causing the fourth switch to equalize signals stored in the first and second storage devices during a fourth interval, the equalized signal being the reference signal.

10. A memory device comprising:

a block of memory cells;

first and second reference cells for storing first and second logic states, respectively, the first and second reference cells being proximate the memory cells; and

a circuit for generating a reference signal during a read operation on selected memory cells in the block, the circuit generating the reference signal by combining outputs of the first and second reference cells.

11. The memory device of claim 10, wherein the first reference cell includes a plurality of first reference elements storing the first logic value;

wherein the second reference cell includes a plurality of second reference elements storing the second logic value; and

wherein the circuit selects a first reference element from the first cell and a second reference element from the second cell.

12. The memory device of claim 11, wherein the selected first and second reference elements lie in same row or column as a selected memory cell in the block.

13. The memory device of claim 10, wherein the first reference cell includes a first reference element storing the first logic value, and the second reference cell includes a second reference element storing the second logic value;

and wherein the first and second reference cells are coupled in parallel.

14. The memory device of claim 13, wherein the first reference cell further includes a third reference element storing the first logic value, the first and third reference elements connected in series;

and wherein the second reference cell further includes a fourth reference element storing the second logic value, the second and fourth reference elements connected in series.

15. A memory device comprising:

a block of memory cells;

first and second storage devices for storing first and second logic states, respectively;

a third storage device for storing a logic value of a selected memory cell in the block; and

a circuit for generating a reference signal during a read operation, the circuit generating the reference signal by combining outputs of the first and second storage devices, and comparing the combined output to an output of the third storage device.

16. The device of claim 15, wherein the circuit includes first, second and third switches and control logic for controlling the switches, the control logic causing the first switch to connect the selected memory cell to the third storage device during a first time interval, the control logic causing the second and third switches to connect the first and second storage devices to the selected memory cell during a second time interval, the control logic causing the second switch to connect the selected memory cell to the first storage device during a third time interval, the control logic causing the third switch to equalize signals stored in the first and second storage devices, the equalized signal being used as the reference signal.

17. The device of claim 15, wherein the circuit includes first, second, third and fourth switches and control logic for controlling the switches, the control logic causing the first switch to connect the selected memory cell to the third storage device during a first time interval, the control logic causing the second switch to connect the first storage device to the selected memory cell during a second time interval, the control logic causing the third switch to connect the selected memory cell to the second storage device during a third time interval, and the control logic causing the fourth switch to equalize signals stored in the first and second storage devices during a fourth interval, the equalized signal being used as the reference signal.