Destination controlled remote DMA engine

• US 6,317,799 B1
• Filed: 04/28/2000
• Issued: 11/13/2001
• Est. Priority Date: 12/15/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Futral, William T., Bell, D. Michael
• Primary Examiner(s): Dharia, Rupal
• Application Number:
  US09/561,287
• Time in Patent Office: 564 Days
• Field of Search: 710/9, 710/22, 710/23, 710/24, 710/26, 710/27, 710/31, 709/212
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Claims

1. A method for accessing memory, the method comprising:

programming a remote DMA engine residing on a first bus from a destination residing on the first bus;

accessing data in a memory with the DMA engine, the DMA engine being embedded in the memory and operating as programmed by the destination; and

transferring the accessed data by the DMA engine to the destination.

2. The method of claim 1, wherein accessing the data includes transferring the data to a write buffer associated with the DMA engine.

3. The method of claim 1, wherein transferring the accessed data includes transferring the data directly to the destination.

4. The method of claim 1, wherein programming the engine includes writing a DMA command block from the destination to the engine.

5. The method of claim 1, wherein programming the engine includes:

writing a DMA command block from the destination to the memory; and

writing a pointer to the command block from the destination to the DMA engine.

6. The method of claim 5, wherein accessing data in the memory includes:

placing the DMA command block on the DMA engine'"'"'s execution list; and

when the command block reaches the top of the execution list, reading the specified data from the memory.

7. The method of claim 1, wherein accessing data in the memory includes:

placing the DMA command block on the DMA engine'"'"'s execution list; and

when the command block reaches the top of the execution list, reading the specified data from the memory.

8. The method of claim 1, wherein transferring the accessed data includes:

issuing a write to a read buffer address for the destination; and

detecting the write to the read buffer address.

9. A method for accessing memory, the method comprising:

writing a DMA command block from an I/O adapter residing on a first bus to a remote DMA engine being embedded in the memory and residing on the first bus;

placing the DMA block on the DMA engine'"'"'s execution list;

when the command block reaches the top of the execution list, reading data from the memory;

issuing a write from the DMA engine to a read buffer address for the I/O adapter;

detecting the write to the read buffer address; and

processing the data.

10. The method of claim 9, wherein writing the DMA command block includes writing a DMA command block specifying at least one of the attributes of the operation, the amount of data to transfer, the location in memory of the data to transfer, and the address to which the DMA engine is to write the data.

11. The method of claim 9, wherein reading data from the memory includes:

generating a series of access requests from the DMA engine to a memory controller for the memory;

processing the access requests; and

writing the data read from the memory to a write buffer associated with the DMA engine.

12. The method of claim 9, wherein reading data from memory includes writing the data from memory to a write buffer associated with the DMA engine.

13. An apparatus comprising:

a memory;

a plurality of buses;

a DMA engine being embedded in the memory and residing on a first of the plurality of buses;

an I/O adapter including a read buffer, the I/O adapter residing on the same first of the plurality buses, and being capable of programming the DMA engine over the first of the plurality of buses.

14. The apparatus of claim 13, wherein the DMA engine is capable of writing data to the read buffer of the I/O adapter.

15. The apparatus of claim 13, wherein the bus implements at least one of a PCI protocol and a SCSI protocol.

16. The apparatus of claim 13, wherein the memory includes at least one DRAM device.

17. The apparatus of claim 13, wherein the memory includes memory devices that are at least one of simply interleaved and complexly interleaved.

18. An apparatus comprising:

a plurality of buses;

an I/O adapter having a read buffer, the I/O adapter residing on a first of the plurality of buses;

a memory;

a DMA engine remote from and programmable by the I/O adapter, the DMA engine being embedded in the memory and residing on the first of the plurality of buses, and being capable of writing data read from the memory to the read buffer in accordance with a programmed command received from the I/O adapter.

19. The apparatus of claim 18, wherein the bus implements at least one of a PCI protocol and a SCSI protocol.

20. The apparatus of claim 18, wherein the memory includes at least one DRAM device.

21. The apparatus of claim 18, wherein the memory includes memory devices that are at least one of simply interleaved and complexly interleaved.

22. An apparatus comprising:

a plurality of buses;

an I/O adapter having a read buffer, the I/O adapter residing a first of the plurality of buses;

a memory including a memory controller;

a DMA engine remote from and programmable by the I/O adapter, the DMA engine being embedded in the memory and residing on the first of the plurality of buses, and being capable of instructing the memory controller to write data read from the memory to the read buffer in accordance with a programmed command received from the I/O adapter.

23. The apparatus of claim 22, wherein the bus implements at least one of a PCI protocol and a SCSI protocol.

24. The apparatus of claim 22, wherein the memory includes at least one DRAM device.

25. The apparatus of claim 22, wherein the memory includes memory devices that are at least one of simply interleaved and complexly interleaved.