Image operation processing apparatus storing discrete data efficiently in a memory and operating method thereof

• US 6,317,817 B1
• Filed: 05/14/1998
• Issued: 11/13/2001
• Est. Priority Date: 05/16/1997
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yoshida, Shinichi, Muramatsu, Tsuyoshi, Shichiku, Ricardo T.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US09/078,491
• Time in Patent Office: 1,279 Days
• Field of Search: 711/202, 711/169, 711/205, 711/206, 711/207, 710/68, 712/201, 395/516, 370/420, 345/515-517
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

An image operation processing apparatus is connected to a memory. The apparatus processes, by accessing the memory, a data packet including instruction information and an address of a prescribed address space. The apparatus realizes an address translation process for translating the address included in an incoming data packet to an address of a partial address space smaller than the prescribed address space. It further realizes a memory access process for accessing the memory in accordance with the address translated by the address translation process. Finally, it performs a process in accordance with the instruction information included in the data packet.

Claims

1. A method of operating an image operation processing apparatus connected to a memory for processing, by accessing to said memory, a data packet including instruction information and an address of a prescribed address space,

said image operation processing apparatus including

address translating means for translating the address included in an incoming data packet to an address of a partial address space smaller than said prescribed address space, and

memory access means for accessing said memory in accordance with the address translated by said address translating means for performing a process in accordance with the instruction information included in the packet,

said method comprising the steps of:

determining address translation by said address translating means such that addresses generated discretely by a prescribed process occupy continuous addresses in said memory after translation by said address translating means;

applying a plurality of data packets holding discrete addresses generated by said prescribed process respectively to said image operation processing apparatus, and storing the data packets at addresses of said memory translated by said address translating means,

wherein said address translating means includes bit shift means for shifting the address included in the incoming data packet to the right by a prescribed number of bits;

the addresses generated by said prescribed process are generated with an interval of 2ⁿ−

1, where n is an integer not smaller than 1; and

said step of determining said address translation includes determining the number of bits of the right shift by said bit shift means to said number n.

2. A method of operating an image operation processing apparatus connected to a memory for processing, by accessing to said memory, a data packet including instruction information and an address of a prescribed address space,

said image operation processing apparatus including

address translating means for translating the address included in an incoming data packet to an address of a partial address space smaller than said prescribed address space, and

memory access means for accessing said memory in accordance with the address translated by said address translating means for performing a process in accordance with the instruction information included in the packet,

said method comprising the steps of:

determining address translation by said address translating means such that addresses generated discretely by a prescribed process occupy continuous addresses in said memory after translation by said address translating means;

applying a plurality of data packets holding discrete addresses generated by said prescribed process respectively to said image operation processing apparatus, and storing the data packets at addresses of said memory translated by said address translating means,

wherein an instruction set, to which the instruction information included in the data packet belongs, includes a specific instruction for performing a prescribed operation between data at a shifted address of said memory determined by shifting the address included in the data packet to the right by a first number of bits and the data included in the data packet, and for writing a result to said shifted address,

said address translating means includes bit shift means for shifting the address included in the incoming data packet to the right by a prescribed number of bits,

addresses generated in said prescribed process are generated at an interval of 2ⁿ−

1, where n corresponds to said first bit number, and

said step of determining said address translation includes the step of determining the number of bits of the right shift by said bit shift means to said number n.

3. A method of operating an image operation processing apparatus connected to a memory for processing, by accessing to said memory, a data packet including instruction information and an address of a prescribed address space,

said image operation processing apparatus including

address translating means for translating the address included in an incoming data packet to an address of a partial address space smaller than said prescribed address space, and

memory access means for accessing said memory in accordance with the address translated by said address translating means for performing a process in accordance with the instruction information included in the packet,

said method comprising the steps of:

determining address translation by said address translating means such that addresses generated discretely by a prescribed process occupy continuous addresses in said memory after translation by said address translating means;

applying a plurality of data packets holding discrete addresses generated by said prescribed process respectively to said image operation processing apparatus, and storing the data packets at addresses of said memory translated by said address translating means,

wherein an instruction set, to which the instruction information included in the data packet belongs, includes a specific instruction for performing a prescribed operation between data at a shifted address in said memory determined by shifting the address included in the data packet to the right by a first number of bits, and for writing a result to said shifted address,

said address translation means includes bit shift means for shifting the address included in the incoming data packet to the right by a prescribed number of bits,

addresses generated in said prescribed process are generated at an interval of 2ⁿ−

1, where n is a positive integer smaller than said first number of bits, and

said step of determining said address translation includes the step of determining the number of bits of the right shift by said bit shift means to said first number of bits.

4. A method of image operation processing for processing, by accessing a memory, a data packet including instruction information and an address of a prescribed address space, comprising the steps of:

determining address translation such that addresses generated discretely by a prescribed process occupy continuous addresses in said memory after said address translation;

storing a plurality of data packets holding the discrete addresses generated by the prescribed process respectively at addresses of said memory translated by said address translation,

wherein the addresses generated by said prescribed process are generated with an interval of 2ⁿ−

1, where n is an integer not smaller than 1, and

said address translation includes a process of shifting to the right the addresses by n bits.

5. A method of image operation processing for processing, by accessing a memory, a data packet including instruction information and an address of a prescribed address space, comprising the steps of:

determining address translation such that addresses generated discretely by a prescribed process occupy continuous addresses in said memory after said address translation;

storing a plurality of data packets holding the discrete addresses generated by the prescribed process respectively at addresses of said memory translated by said address translation,

wherein an instruction set, to which the instruction information included in the data packet belongs, includes a specific instruction for performing a prescribed operation between data at a shifted address in said memory determined by shifting the address included in the data packet to the right by a first number of bits and the data included in the data packet, and for writing a result to said shifted address,

the addresses generated by said prescribed process are generated with an interval of 2ⁿ−

1, where n corresponds to said first number of bits, and

said address translation includes a process of shifting the addresses to the right by said n bits.

6. A method of image operation processing for processing, by accessing a memory, a data packet including instruction information and an address of a prescribed address space, comprising the steps of:

determining address translation such that addresses generated discretely by a prescribed process occupy continuous addresses in said memory after said address translation;

storing a plurality of data packets holding the discrete addresses generated by the prescribed process respectively at addresses of said memory translated by said address translation,

wherein an instruction set to which instruction information included in the data packet belongs includes a specific instruction for performing a prescribed operation between data at a shifted address in said memory determined by shifting the address included in the data packet to the right by a first number of bits, and the data included in the data packet, and for writing a result to said shifted address,

the addresses generated by said prescribed process are generated with an interval of 2ⁿ−

1, where n is a positive integer smaller than said first number of bits, and

said address translation includes a process of shifting the addresses to the right by said first number of bits.