Method and apparatus for performing integer operations in response to a result of a floating point operation

• US 6,317,824 B1
• Filed: 03/27/1998
• Issued: 11/13/2001
• Est. Priority Date: 03/27/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Scott, Wayne H., Thakkar, Shreekant S., Roussel, Patrice
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): PATEL, GAUTAM
• Application Number:
  US09/049,827
• Publication Number:
  US 20010049780A1
• Time in Patent Office: 1,327 Days
• Field of Search: 712/239, 712/566, 712/222, 712/569, 708/212, 708/495, 708/525, 340/146.2
• US Class Current: 712/222
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers

Abstract

A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and conversion of the results to data of a second size and format by eliminating redundant data. The present invention is useful, for example, when comparisons are performed on floating point data that is typically larger (e.g., 64 bits) than integer data (e.g., 32 bits) and integer operations are preformed based on the result. Because many processors branch based on integer data, the comparison results stored as floating point data must be transferred to an integer register prior to branching. The present invention takes advantage of redundancy of the floating point comparison results to transfer enough data to convey the comparison result to integer registers with a single instruction.

Claims

1. In a computer system, a method comprising:

performing an operation on data stored in a packed floating point format;

extracting data from a result of the operation, the result stored in the packed floating point format, wherein the extracted data comprises one or more bits representing redundant data for each number represented in the packed floating point result;

transferring the one or more bits for each number of the packed floating point result a common integer register; and

determining whether a branching condition is met based on the bits stored in the integer register.

2. The method of claim 1, wherein performing an operation on packed floating point data comprises performing a comparison of two sets of packed floating point data.

3. The method of claim 1, wherein extracting data comprises setting a bit in a result mask register equal to a corresponding most significant bit of each associated packed floating point data value.

4. The method of claim 1, wherein transferring comprises transferring the set of one or more bits from a floating point register to an integer register.

5. A circuit comprising:

a first set of registers to store data in a packed floating point format;

a first arithmetic unit coupled to the first set of registers to perform a compare operation on data stored in the first set of registers and to store a result as a packed floating point value in one of the first set of registers, the first arithmetic unit further to extract a set of bits from the result, where each bit in the set of bits represents redundant bits in each number represented by the packed floating point format;

a second set of registers to store data in an integer format;

a transfer circuit coupled between the first set of registers and the second set of registers, the transfer circuit to transfer the set of bits to one of the integer registers; and

a second arithmetic unit to cause branching operations to be performed based on the set of bits stored in the integer registers.

6. An apparatus comprising:

means for performing an operation on data stored in a packed floating point format;

means for extracting data from a result of the operation, the result stored in the packed floating point format, wherein the extracted data comprises one or more bits representing redundant data for each number represented in the packed floating point result;

means for transferring the one or more bits for each number of the packed floating point result a common integer register; and

means for determining whether a branching condition is met based on the bits stored in the integer register.

7. The apparatus of claim 6, wherein the means for performing an operation on packed floating point data comprises means for performing a comparison of two sets of packed floating point data.

8. The apparatus of claim 6, wherein the means for extracting data comprises setting a bit in a result mask register equal to a corresponding most significant bit of each associated packed floating point data value.

9. The apparatus of claim 6, wherein the means for transferring comprises means for transferring the set of one or more bits from a floating point register to an integer register.

10. A graphics display system comprising:

a bus;

a display device coupled to the bus; and

a processor coupled to the display device, the processor having a plurality of registers to store packed floating point data and integer data, the processor further comprising circuitry to extract a set of one or more bits of data from one of the registers that stores floating point data and to transfer the extracted bits to an integer register to perform an integer operation, wherein the set of one or more bits comprises at least one bit corresponding to redundant data in each number represented by the packed floating point register, the processor further to cause the display device to change what is displayed in response to the integer operation.

11. The graphics display system of claim 10, wherein the packed floating point data represents a portion of what is displayed by the display device.

12. The graphics display system of claim 10, wherein the processor extracts a most significant bit from each value represented by the packed floating point data.

13. An article comprising a machine-readable medium having stored thereon sequences of instructions that, when executed, cause one or more processors to:

perform an operation on data stored in a packed floating point format;

extract data from a result of the operation, the result stored in the packed floating point format, wherein the extracted data comprises one or more bits representing redundant data for each number represented in the packed floating point result;

transfer the one or more bits for each number of the packed floating point result a common integer register; and

determine whether a branching condition is met based on the bits stored in the integer register.

14. The article of claim 13, wherein the sequences of instructions that cause the one or more processors to perform an operation on packed floating point data comprises sequences of instructions that, when executed, cause the one or more processors to perform a comparison of two sets of packed floating point data.

15. The article of claim 13, wherein the sequences of instructions that cause the one or more processors to extract data from a result of the operation stored in the packed floating point format comprises sequences of instructions that, when executed, cause the one or more processors to set a bit in a result mask register equal to a corresponding most significant bit of each associated packed floating point data value.

16. The article of claim 13, wherein the sequences of instructions that cause the one or more processors to transfer the subset of bits to an integer register comprises sequences of instructions that, when executed, cause the one or more processors to transfer the set of one or more bits from a floating point register to an integer register.