Method of and apparatus for controlling supply of power to a peripheral device in a computer system

• US 6,317,839 B1
• Filed: 01/19/1999
• Issued: 11/13/2001
• Est. Priority Date: 01/19/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wells, Robert Marion
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/234,142
• Time in Patent Office: 1,029 Days
• Field of Search: 713/300-340
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3221 of disk drive devices
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G11B 19/20 Driving; Starting; Stopping; Control thereof
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A peripheral device, such as a data storage device, is employed in a computer system having one or more computers. The computer system includes an interface architecture, such as Fiber channel or Serial Storage Architecture (SSA), providing a continuously clocked serial link. The data storage device includes a power supply and data storage components, such as disk drives, carried in a housing. One or more data communication interfaces, each of which is adapted for coupling with a computer through conductors, are carried on the housing and coupled to the data storage components. The data storage components have a substantially powered up state and a substantially powered down state which is entered in response to a power down signal. Detector circuitry is operative to detect a clock signal loss at each one of the data communication interfaces and to produce the power down signal responsive to the detection.

Claims

1. A data storage device for utilization in a computer system having one or more computers and communicative over a continuously clocked serial link, said data storage device comprising:

a housing;

a power supply;

data storage components, said data storage components carried in said housing, said data storage components having a substantially powered up state and a substantially powered down state, said data storage components operative to enter the substantially powered down state responsive to a power down signal;

one or more data communication interfaces, said data communication interfaces carried on said housing and coupled to said data storage components, each of said data communication interfaces adapted for coupling with a computer through conductors; and

detector circuitry, said detector circuitry operative to detect a loss of a clock signal for an active communication link at each one of said data communication interfaces and to produce the power down signal in response thereto.

2. A data storage device according to claim 1, wherein said detector circuitry is operative to detect the clock signal loss at each one of said data communication interfaces designated for computer communication.

3. A data storage device according to claim 1, wherein said detector circuitry is operative to detect a clock signal on at least one of said data communication interfaces and to terminate the power down signal in response thereto.

4. A data storage device according to claim 1, wherein said data storage components comprise at least one of a disk drive, a CD-ROM drive, a tape drive, and an optical drive.

5. A data storage device according to claim 1, wherein said power supply is adapted for coupling with a power source that is separate and apart from a power source of the computers.

6. A data storage device according to claim 1, wherein said data storage device is configured in accordance with one of Fibre channel and Serial Storage Architecture (SSA) standards.

7. A data storage device according to claim 1, wherein said detector circuitry comprises:

at least one diode coupled to a data communication interface; and

a comparator having a first input coupled to said at least one diode and a second input coupled to a reference voltage.

11. A peripheral device according to claim 7, wherein said peripheral device is configured in accordance with Fibre channel standards.

12. A peripheral device according to claim 7, wherein said peripheral device is configured in accordance with Serial Storage Architecture (SSA) standards.

8. A peripheral device, comprising:

a housing;

peripheral device components, said peripheral device components disposed in said housing, said peripheral device components having a substantially powered up state and a substantially powered down state;

a power supply, said power supply operative to supply electrical power to said peripheral device components when in the substantially powered up state;

at least one data communication interface, said at least one data communication interface carried with said housing and coupled to said peripheral device components, each one of said at least one data communication interface adapted for coupling with a computer through conductors; and

detector circuitry, said detector circuitry operative to cause said peripheral device components to enter the substantially powered down state in response to detecting communication link inactivity at each one of said at least one data communication interface.

9. A peripheral device according to claim 8, further comprising:

said detector circuitry operative to cause said peripheral device components to enter the substantially powered up state in response to detecting communication link activity on at least one of said at least one data communication interfaces.

10. A peripheral device according to claim 8, further comprising:

a power source interface of said power supply, said power source interface adapted for coupling with a power source.

13. A method of controlling a supply of electrical power to a peripheral device, the peripheral device having peripheral device components operative for data communication with one or more computers, the peripheral device operable from a power source separate and apart from those of the computers, the method comprising:

supplying electrical power to the peripheral device components so that the peripheral device components are substantially operative;

detecting communication link inactivity at each one of a plurality of data communication interfaces; and

in response to detecting the communication link inactivity, terminating supply of electrical power to the peripheral device components so that the peripheral device components are substantially inoperative.

14. A method according to claim 13, further comprising:

detecting communication link activity on at least one of the plurality of data communication interfaces; and

in response to detecting the communication link activity, supplying electrical power to the peripheral device components so that the peripheral device components are substantially operative.

15. A method according to claim 13, wherein detecting the communication link inactivity comprises detecting a clock signal loss.

16. A method according to 13, wherein detecting the communication link inactivity comprises detecting a clock signal loss and detecting the communication link activity comprises detecting a clock signal.

17. A method according to claim 13, wherein supplying electrical power to the peripheral device components comprises supplying electrical power to data storage components of the peripheral device.

18. A computer system, comprising:

at least one computer, including;

a first housing;

first electronic components, said first electronic components disposed in said first housing and substantially operative in a computer ON state and substantially non-operative in a computer OFF state;

a first power source interface, said first power source interface adapted for coupling with a first power source that supplies electrical power to said first electronic components in the computer ON state;

a first actuable switch, said first actuable switch carried on said first housing and actuable to an ON position and to an OFF position for invoking the computer ON and OFF states, respectively;

a data transmitter, said data transmitter operative to generate signals at a transmitter output in the computer ON state and to terminate generation of the signals in the computer OFF state;

a first data communication interface, said first data communication interface coupled to said transmitter output;

a peripheral device, including;

a second housing separate and apart from said first housing;

peripheral device components, said peripheral device components carried on said second housing, said peripheral device components substantially operative in a peripheral device ON state and substantially non-operative in a peripheral device OFF state;

a second power source interface, said second power source interface adapted for coupling with a second power source that supplies electrical power to said peripheral device components in the peripheral device ON state and that is separate and apart from the first power source;

a plurality of data communication interfaces, said plurality of data communication interfaces carried with said housing, each of said plurality of data communication interfaces adapted for coupling with one said first data communication interface of said plurality of computers through cables; and

detector circuitry, said detector circuitry operative to detect the loss of a clock signals for an active communication link from each of said computers and to set said peripheral device in the peripheral device OFF state in response thereto.

19. The computer system according to claim 18, wherein said detector circuitry is operative to detect the signals from at least one of said plurality of computers and to set said peripheral device to the peripheral device ON state in response thereto.

20. The computer system according to claim 18, wherein each said data transmitter of said plurality of computers is operative to generate signals in the computer ON state comprising a continuous clock signal.