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Computer system using stop clock function of CPU to enter low power state

  • US 6,317,841 B1
  • Filed: 05/08/1998
  • Issued: 11/13/2001
  • Est. Priority Date: 05/30/1995
  • Status: Expired due to Fees
First Claim
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1. A computer system comprising:

  • a central processing unit (CPU) coupled to receive a signal which stops an internal clock of the CPU;

    means for periodically asserting the signal to set the CPU in a low power state; and

    a circuit, coupled to the CPU, for blocking the assertion of a system event request with respect to the CPU while the signal is asserted, wherein the circuit holds the system event request, breaks the assertion of the signal in response to the held system event request, and then outputs the held system event request to the CPU after the assertion of the signal is broken.

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