Method and apparatus for irregular datapath placement in a datapath placement tool

• US 6,317,863 B1
• Filed: 09/30/1997
• Issued: 11/13/2001
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Segal, Russell B.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/941,893
• Time in Patent Office: 1,505 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 716/2, 716/8, 716/9, 716/10, 716/11, 716/12, 716/13, 716/14, 716/1
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method and apparatus for datapath placement of irregular logic, while still allowing control of wire lengths. The method and apparatus allow use of a objective, called a directed placement objective, that causes a logic gate to be placed at or near a coordinate, such as an input or output pin connected to the gate.

Claims

1. A placement method for placing elements of a circuit representation of an integrated circuit, said circuit representation stored in a memory of a computer system, said method comprising the steps of:

a) spatially ordering each of a plurality of function blocks of a datapath of said circuit representation in order to minimize bus connections between said plurality of function blocks;

b) determining an area for each function block of said plurality of function blocks of said datapath;

c) determining a rough floorplan of said plurality of function blocks of said datapath based on said area for each function block and based on a spatial order determined by step a);

d) performing gridded placement to place regular gates of said plurality of function blocks wherein each regular gate is placed at a spatial location within its associated function block;

e) performing directed placement to place irregular gates of said plurality of function blocks and, in addition, performing directed placement to place gates having connections between datapath blocks, wherein each gate placed by step e) is placed at a location within its associated function block, said step e) comprising the steps of;

e1) spacing input/output pins along a respective function block at approximately equal spacing; and

e2) placing each irregular gate and each gate having connections between datapath blocks, in a location near an input/output pin that is associated with said each gate.

2. A method as described in claim 1 wherein said step e1) places said input/output pins for said respective function block at equal spatial intervals.

3. A method as described in claim 1 wherein said step e1) places said input/output pins for said respective function block at unequal spatial intervals.

4. A method as described in claim 1 wherein said step c) comprises the step of c1) determining that said plurality of function blocks are of different heights.

5. A method as described in claim 1 wherein said step c) comprises the step of c1) determining that said plurality of function blocks are of a same height.

6. A method as described in claim 1 further comprising the step of generating said circuit representation using a logic synthesis tool.

7. A method as described in claim 1 further comprising the step of grouping some of said plurality of function blocks in advance of said step a).

8. A computer usable medium having computer readable code embodied therein for causing a method of placement of an integrated circuit design having a circuit representation which is stored in a memory of a computer system, said method comprising the steps of:

a) spatially ordering each of a plurality of function blocks of a datapath of said circuit representation in order to minimize bus connections between said plurality of function blocks;

b) determining an area for each function block of said plurality of function blocks of said datapath;

c) determining a rough floorplan of said plurality of function blocks of said datapath based on said area for each function block and based on a spatial order determined by step a);

d) performing gridded placement to place regular gates of said plurality of function blocks wherein each regular gate is placed at a spatial location within its associated function block;

e) performing directed placement to place irregular gates of said plurality of function blocks and, in addition, performing directed placement to place gates having connections between datapath blocks, wherein each gate placed by step e) is placed at a location within its associated function block, said step e) comprising the steps of;

e1) spacing input/output pins along a respective function block at approximately equal spacing; and

e2) placing each irregular gate and each gate having connections between datapath blocks, in a location near an input/output pin that is associated with said each gate.

9. A computer usable medium as described in claim 8 wherein said step e1) of said method places said input/output pins for said respective function block at equal spatial intervals.

10. A computer usable medium as described in claim 8 wherein said step e1) of said method places said input/output pins for said respective function block at unequal spatial intervals.

11. A computer usable medium as described in claim 8 wherein said step c) of said method comprises the step of c1) determining that said plurality of function blocks are of different heights.

12. A computer usable medium as described in claim 8 wherein said step c) of said method comprises the step of c1) determining that said plurality of function blocks are of a same height.

13. A computer usable medium as described in claim 8 wherein said method further comprises the step of generating said circuit representation using a logic synthesis tool.

14. A computer usable medium as described in claim 8 wherein said method further comprises the step of grouping some of said plurality of function blocks in advance of said step a).