Real time processor optimized for executing JAVA programs

• US 6,317,872 B1
• Filed: 04/06/1998
• Issued: 11/13/2001
• Est. Priority Date: 07/11/1997
• Status: Expired due to Term

• Current Assignee: Rockwell Collins, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Rockwell Collins, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Hiratzka, T. Douglas, Kamin, Raymond A., Hardin, David S., Gee, John K., Mass, Allen P., Greve, David A., Mykris, Nick M., Masters, Michael H.
• Primary Examiner(s): Chaki, Kakali
• Assistant Examiner(s): DAM, TUAN QUANG
• Application Number:
  US09/056,048
• Time in Patent Office: 1,317 Days
• Field of Search: 395/707, 395/705, 395/702, 395/706, 395/708, 711/6, 711/203, 711/206, 711/209, 712/202, 712/200, 712/208, 712/209, 707/206, 707/205
• US Class Current: 717/152
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99957 Garbage collection

Abstract

An improved computer architecture and system advantageously combine the beneficial characteristics of a high level object oriented programming language with an optimized processor for efficient application to real time embedded computing problems. Additionally, an improved method for resolving symbolic references in code generated by compiling source code written in an object oriented programming language to the corresponding logical memory addresses stores look-up information with the object itself after the first encounter of a given symbolic reference, whereby the logical memory address information is available for subsequent encounters of the symbolic reference, and whereby no modification of the program instructions containing the symbolic reference is necessary. In a preferred embodiment, the Java™ programming language is used.

Claims

1. A computer system comprising:

(a) a compiler for compiling a high level source code to generate an intermediate code; and

(b) a microprocessor system for executing said intermediate code, said microprocessor system comprising a microprocessor and an instruction set so that said microprocessor system is capable of executing said intermediate code as the native code of the microprocessor without a software interpreter;

wherein said intermediate code is characterized in that it does not require a direct knowledge of the microprocessor environment;

wherein said intermediate code comprises a real time embedded program.

2. The computer system according to claim 1 wherein said intermediate code retains at least some symbolic references of its corresponding source code.

3. The computer system according to claim 1 wherein said source code is selected from the group consisting of the source codes of C, C+, C++ and Java.

4. The computer system according to claim 1 wherein said source code is selected from the group consisting of the source codes of C, C+ and C++.

5. The computer system according to claim 1 wherein said microprocessor employs stack-oriented addressing.

6. The computer system according to claim 5 wherein a plurality of different microcoded instruction sets may be employed without substantially altering the fundamental architecture of the computer system.

7. The computer system according to claim 5 wherein the microprocessor is a Rockwell Advanced Architecture MicroProcessor with at least 16 bit addressing.

8. The computer system according to claim 1 wherein said intermediate code uses primarily symbolic references to stored information.

9. The computer system of claim 1 wherein said intermediate code comprises a transportation application.

10. The computer system of claim 9 wherein the computer system is embedded in avionic equipment.

11. A computer system comprising:

(a) a compiler for compiling a high level source code to generate an intermediate code; and

(b) a microprocessor system for executing said intermediate code, said microprocessor system comprising a microprocessor and an instruction set so that said microprocessor system capable of executing said intermediate code as the native code of the microprocessor without a software interpreter;

wherein said intermediate code is characterized in that it does not require a direct knowledge of the microprocessor environment; and

wherein said intermediate code retains at least some of the symbolic characteristics of its corresponding source code.

14. The method according to claim 11 wherein no modification of said sequence of instructions is made.

12. A computer system comprising:

(a) a compiler for compiling a high level source code to generate an intermediate code;

(b) a microprocessor system for executing said intermediate code, said microprocessor system comprising a microprocessor and an instruction set so that said microprocessor system is capable of executing said intermediate code as the native code of the microprocessor without a software interpreter;

wherein said intermediate code is characterized in that it does not require a direct knowledge of the microprocessor environment, wherein said compiler is capable of generating Java bytecodes and wherein said source code is selected from the group consisting of the source codes of C, C+ and C++.

15. The method according to claim 12 wherein said sequence of instructions are stored in read-only memory.

13. A computer system comprising:

(a) a compiler for compiling a high level source code to generate an intermediate code; and

(b) a microprocessor system for executing said intermediate code, said microprocessor system comprising a microprocessor and an instruction set so that said microprocessor system capable of executing said intermediate code as the native code of the microprocessor without a software interpreter;

wherein said intermediate code is characterized in that it does not require a direct knowledge of the microprocessor environment; and

wherein said intermediate code uses primarily symbolic references to stored information.

16. The method according to claim 13 wherein said time critical computer program comprises a real time embedded program.

17. The method according to claim 16 wherein said intermediate comprises a real time embedded program.

20. The computer system claim 17, wherein the intermediate level instructions primarily use symbolic references to stored information.

21. The computer system of claim 17, wherein a microprocessor employing stack-oriented addressing is used to execute the native level instructions.

22. The computer system of claim 17, wherein the intermediate level instructions are compiled from the source code of an object-oriented language.

23. The computer system of claim 17, wherein the intermediate level instructions are compiled from the source code of a computer language selected from the group consisting of Java, C, C+ and C++.

24. The computer system of claim 17, wherein a Rockwell Advanced Architecture Microprocessor with at least 16 bit addressing is used to execute the native level instructions.

18. A computer system comprising

(a) a first memory wherein intermediate level instructions are stored;

(b) a second memory wherein native level instructions are stored; and

(c) circuitry for selecting a set of native level instructions to execute in response to each intermediate level instruction without a software interpreter; and

wherein the intermediate level instructions retain at least some of the symbolic characteristics of their source code.

19. The computer system of claim 18, wherein the intermediate level instructions primarily use symbolic references to store information.

25. A computer system comprising

(a) a first memory wherein intermediate level instructions are stored;

(b) a second memory wherein native level instructions are stored; and

(c) circuitry for selecting a set of native level instructions to execute in response to each intermediate level instruction without a software interpreter; and

wherein the intermediate level instructions primarily use symbolic references to stored information.

26. A computer system comprising:

(a) a first memory wherein intermediate level instructions are stored;

(b) a second memory wherein native level instructions are stored; and

(c) circuitry for selecting a set of native level instructions to execute in response to each intermediate level instruction without a software interpreter; and

wherein a Rockwell Advanced Achitecture Microprocessor with at least 16 bit addressing is used to execute the native level instructions.

27. A computer system comprising:

(a) a first memory wherein intermediate level instructions are stored;

(b) a second memory wherein native level instructions are stored; and

(c) circuitry for selecting a set of native level instructions to execute in response to each intermediate level instruction without a software interpreter; and

wherein a microprocessor is used to execute the microcoded native level instructions and wherein the native level instruction set may be changed without altering the fundamental architecture of the computer system.

28. A computer system comprising:

(a) a first memory wherein intermediate level instructions are stored;

(b) a second memory wherein native level instructions are stored; and

(c) circuitry for selecting a set of native level instructions to execute in response to each intermediate level instruction without a software interpreter; and

wherein memory resident objects are partitioned into garbage-collectible and non-garage collectible types;

wherein the system determines which of the garbage-collectible types will be needed during the remainder of the program execution; and

wherein the memory occupied by the unneeded garbage-collectible objects is deallocated.

29. A computer system comprising

(a) a first memory wherein intermediate level instructions are stored;

(b) a second memory wherein native level instructions are stored; and

(c) circuitry for selecting a set of native level instructions to execute in response to each intermediate level instruction without a software interpreter; and

whereinsymbolic references are resolved to logical references by a method comprising the steps of;

(a) providing an index which links all symbolically referenced items of information to a corresponding logical memory address;

(b) interpreting said intermediate level instructions;

(c) upon a first encounter of any symbolic reference within said intermediate level instructions, resolving the symbolic reference to a logical reference by searching the index and retrieving location information;

(d) storing the logical reference location information with the referenced object;

whereby subsequent encounters of any previously resolved symbolic references may use previously retrieved location information stored with the object. memory for storing the intermediate code and a second memory for storing native level code, wherein the executing step includes selecting the native level code in response to the intermediate code.

30. A computer system comprising:

(a) a compiler for compiling a high level source code to generate an intermediate code; and

(b) a microprocessor system for executing said intermediate code, said microprocessor system comprising a microprocessor and an instruction set so that said microprocessor system capable of executing said intermediate code as the native code of the microprocessor without a software interpreter;

wherein memory resident objects are partitioned into garbage-collectible and non-garbage collectible types;

wherein the system determines which of the garbage-collectible types will be needed during the remainder of the program execution; and

wherein the memory occupied by the unneeded garbage-collection objects is deallocated.

31. A computer system comprising:

(a) a compiler for compiling a high level source code to generate an intermediate code; and

(b) a microprocessor system for executing said intermediate code, said microprocessor system comprising a microprocessor and an instruction set so that said microprocessor system capable of executing said intermediate code as the native code of the microprocessor without a software interpreter;

wherein said intermediate code is characterized in that it does not require a direct knowledge of the microprocessor environment;

wherein symbolic references are resolved to logical references by a method comprising the steps of;

(a) providing an index which links all symbolically referenced items of information to a corresponding logical memory address;

(b) interpreting said intermediate level instructions;

(c) upon a first encounter of any symbolic reference within said intermediate level instructions, resolving the symbolic reference to a logical reference by searching the index and retrieving location information;

(d) storing the logical reference location information with the referenced object;

whereby subsequent encounters of any previously resolved symbolic references may use previously retrieved location information stored with the object.

32. A method of executing a high level source code, comprising:

compiling the high level source code to generate an intermediate code, the intermediate code does not require knowledge of a microprocessor environment;

executing the intermediate code with a microprocessor system, the microprocessor system comprising an instruction set so that said microprocessor system capable of executing the intermediate code without a software interpreter,

wherein the intermediate code comprises a real time embedded program.

33. The method of claim 32, wherein the microprocessor system includes a first memory for storing the intermediate code and a second memory for storing native level code, wherein the executing step includes selecting the native level code in response to the intermediate code.

34. A method of executing a high level source code, comprising:

compiling the high level source code to generate an intermediate code, the intermediate code does not require knowledge of a microprocessor environment;

executing the intermediate code with a microprocessor system, the microprocessor system comprising an instruction set so that said microprocessor system capable of executing the intermediate code without a software interpreter;

wherein the microprocessor system includes a first memory for storing the intermediate code and a second memory for storing native level code, wherein the executing step includes selecting the native level code in response to the intermediate code;

wherein the executing step includes;

(a) providing an index which links all symbolically referenced items of information to a corresponding logical memory address;

(b) interpreting said intermediate level instructions;

(c) upon a first encounter of any symbolic reference within said intermediate level instructions, resolving the symbolic reference to a logical reference by searching the index and retrieving location information;

(d) storing the logical reference location information with the referenced object;

whereby subsequent encounters of any previously resolved symbolic references may use previously retrieved location information stored with the object.

35. A computer system comprising:

(a) a compiler means for compiling a high level source code to generate an intermediate code; and

(b) a microprocessor system means for executing said intermediate code, said microprocessor system comprising a microprocessor and an instruction set so that said microprocessor system capable of executing said intermediate code as the native code of the microprocessor means without a software interpreter;

wherein said intermediate code is characterized in that it does not require a direct knowledge of the microprocessor environment, wherein the intermediate code comprises a real time embedded program.