Structure and method for producing low leakage isolation devices

• US 6,319,794 B1
• Filed: 10/14/1998
• Issued: 11/20/2001
• Est. Priority Date: 10/14/1998
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Kleinhenz, Richard, Ho, Herbert L., Natzle, Wesley C., Chen, Tze-Chiang, Mandelman, Jack A., Akatsu, Hiroyuki, Economikos, Laertis
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): GUERRERO, MARIA F
• Application Number:
  US09/172,697
• Time in Patent Office: 1,133 Days
• Field of Search: 438/425, 438/421, 438/426, 438/424, 438/439, 438/427, 438/444, 438/445, 438/700
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.

Claims

1. A process for forming a substantially divot-free isolation device within an integrated circuit device, said process comprising the steps of:

a) forming an oxide film on a semiconductor surface of a semiconductor substrate;

b) depositing a first silicon nitride film on said oxide film to form a device substrate, said first silicon nitride film having a top surface;

c) forming a trench within said device substrate, said trench extending

i) through said first silicon nitride film and said oxide film, and

ii) into said semiconductor substrate, said trench having a trench bottom and a trench wall;

d) forming an oxide liner on at least said trench wall;

e) forming a silicon nitride liner film over said oxide liner on at least said trench wall and forming a silicon nitride cover film having an upper surface over said first silicon nitride film;

f) filling said trench with a dielectric film, said dielectric film having an upper surface extending above said upper surface of said silicon nitride cover film, and forming an intersection between said isolation device and said semiconductor surface;

g) substantially planarizing said isolation device by removing portions of said dielectric film which extend above a plane formed by said upper surface of said silicon nitride cover film, wherein an upper level of said dielectric film is substantially planar with said upper surface of said silicon nitride cover film;

h) removing said silicon nitride cover film and said first silicon nitride film and recessing said silicon nitride liner film below said semiconductor surface to form a divot along said trench wall;

i) substantially filling said divot with an insulating material; and

j) removing said oxide film;

wherein a substantially continuous surface is produced at said intersection.

2. The process as in claim 1, further comprising the step of etching said device using a gaseous mixture of hydrofluoric acid and ammonium prior to the step of substantially filling said divot.

3. The process as in claim 1, wherein said step i) comprises the steps of:

i1) partially filling said divot with a polysilicon film; and

i2) oxidizing said polysilicon film.

4. The process as in claim 1, wherein said step of filling said trench with said dielectric film comprises a low pressure chemical deposition of a TEOS film.

5. The process as in claim 1, wherein said step of filling said trench with said dielectric film comprises depositing a TEOS film.

6. The process as in claim 1, wherein said step of filling said trench with said dielectric film comprises an ozone assisted chemical deposition of a TEOS film.

7. The process of claim 1, wherein said semiconductor substrate comprises a silicon substrate.

8. The process of claim 1, wherein said step d) comprises forming a thermally-grown oxide film on at least said trench wall.

9. The process of claim 1, wherein said step h) comprises chemically etching using phosphoric acid.

10. The process as in claim 1, wherein said step of substantially planarizing comprises chemical mechanical polishing.

11. The process as in claim 1, further comprising the step of:

c1) selectively removing a portion of the first silicon nitride film adjacent said trench.

12. The method as in claim 1, wherein said step a) comprises thermally oxidizing said semiconductor substrate, said oxide film consuming a portion of said semiconductor substrate.

13. The process as in claim 1, wherein said step i) comprises filling said divot with a filler oxide film.

14. The process as in claim 1, wherein said step of removing said oxide film comprises chemically etching said oxide film using a gaseous mixture of hydrofluoric acid and ammonium.

15. The process as in claim 13, wherein said filler oxide film comprises a filler TEOS film.

16. The process as in claim 14, wherein a solid product layer is formed over said oxide film, said solid product layer containing silicon, and being partially resistant to diffusion of hydrofluoric acid, and wherein said method of chemically etching is self-limiting.

17. A process for forming a substantially divot-free isolation device within an integrated circuit device, said process comprising the steps of:

a) forming a first oxide film over a semiconductor surface of a semiconductor substrate;

b) depositing a first silicon nitride film over said first oxide film to form a device substrate, said first silicon nitride film having a top surface;

c) forming a trench within said device substrate, said trench extending

i) through said first silicon nitride film and said first oxide film, and

ii) into said semiconductor substrate, said trench having a trench bottom and a trench wall;

d) forming an oxide liner on at least said trench wall;

e) forming a silicon nitride liner film over said oxide liner on at least said trench wall and forming a silicon nitride cover film having an upper surface over said first silicon nitride film;

f) filling said trench with a dielectric film, said dielectric film having an upper surface extending above said upper surface of said silicon nitride cover film, and forming an intersection between said isolation device and said semiconductor surface;

g) substantially planarizing said isolation device by removing portions of said dielectric film which extend above a plane formed by said upper surface of said silicon nitride cover film, an upper level of said dielectric film substantially planar with said upper surface of said silicon nitride cover film;

h) removing said silicon nitride cover film and said first silicon nitride film and recessing said silicon nitride liner film below said semiconductor surface to form a divot along said trench wall;

i) removing said first oxide film;

j) forming a second oxide film on at least said semiconductor surface;

k) substantially filling said divot with an insulating material; and

l) removing said second oxide film to substantially expose said semiconductor surface;

wherein a substantially continuous surface is produced at said intersection.

18. The method as in claim 17, wherein said step j) comprises thermally oxidizing said semiconductor surface.

19. A process for forming a substantially divot-free isolation device within an integrated circuit device, said process comprising the steps of:

a) forming an oxide film on a semiconductor surface of a semiconductor substrate;

b) depositing a first silicon nitride film on the oxide film to form a device substrate, the first silicon nitride film having a top surface;

c) forming a trench within the device substrate, the trench extending i) through the first silicon nitride film and the oxide film, and ii) into the semiconductor substrate, the trench having a trench bottom and a ii trench wall;

d) forming an oxide liner on at least the trench wall;

e) forming a silicon nitride liner film over the oxide liner on at least the trench wall and forming a silicon nitride cover film having an upper surface over the first silicon nitride film;

f) filling the trench with a dielectric film, the dielectric film having an upper surface extending above the upper surface of the silicon nitride cover film, and forming an intersection between the isolation device and the semiconductor surface;

g) substantially planarizing the isolation device by removing portions of the dielectric film which extend above a plane formed by the upper surface of the silicon nitride cover film, wherein an upper level of the dielectric film is substantially planar with the upper surface of the silicon nitride cover film;

h) removing the silicon nitride cover film and the first silicon nitride film;

i) recessing the silicon nitride liner film below the semiconductor surface to form a divot between at least a portion of the trench wall and the dielectric film;

j) substantially filling the divot with an insulating material; and

k) removing the oxide film,

wherein a substantially continuous surface is produced at the intersection between the isolation device and the semiconductor surface.