Enhanced interconnection to ceramic substrates

• US 6,319,829 B1
• Filed: 08/18/1999
• Issued: 11/20/2001
• Est. Priority Date: 08/18/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reddy, Srinivasa S. N., Pasco, Robert W., Vallabhaneni, Rao V.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lytle, Craig P.
• Application Number:
  US09/376,599
• Time in Patent Office: 825 Days
• Field of Search: 438/106-109, 438/121, 257/678, 257/700, 257/703, 257/708, 439/91, 439/66, 439/591
• US Class Current: 438/678
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/10378 Interposers
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor chip interposer increases fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE. The semiconductor chip interposer includes a thin metal plate having a plurality of through holes, the thin metal plate having a TCE intermediate the relatively high TCE and the relatively low TCE. An insulation coating on the thin metal plate is also included on walls of the through holes. An electrical conductive material fills each of the insulated through holes for electrical interconnection between the first component and the second component.

Claims

1. A semiconductor chip interposer for increasing fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE, comprising:

a thin substrate having a TCE intermediate the relatively high TCE and the relatively low TCE and a plurality of through holes that are electrically insulated from one another, wherein the substrate is a thin metal plate having a thickness in the range of 2-8 mil; and

an electrical conductive material filling each of the insulated through holes for electrical interconnection between the first component and the second component.

2. The interposer of claim 1 wherein the substrate includes an insulation coating on said thin metal plate including on walls of the through holes.

3. The interposer of claim 2 wherein the insulation coating comprises an oxide coating.

4. A semiconductor chip interposer for increasing fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE, comprising:

a thin metal plate having a plurality of through holes, the thin metal plate having a TCE intermediate the relatively high TCE and the relatively low TCE;

an insulation coating on said thin metal plate including on walls of the through holes; and

an electrical conductive material filling each of the insulated through holes for electrical interconnection between the first component and the second component.

5. The interposer of claim 4 wherein the thin metal plate is a metal foil having a thickness in the range of 2-8 mil.

6. The interposer of claim 4 wherein the insulation coating comprises an oxide coating.

7. The interposer of claim 4 wherein the chip comprises a multi-chip module and the interposer comprises a segmented interposer.

8. The interposer of claim 4 further comprising conductive I/O pads on either side of the through openings electrically connected to the conductive material.

9. The interposer of claim 8 wherein the second component is a glass-ceramic substrate having I/O pads and the interposer is joined to the substrate by co-sintering the substrate I/O pads and the interposer I/O pads.

10. The interposer of claim 8 further comprising conductive pins brazed to I/O pads on one side of the interposer.

11. The interposer of claim 10 wherein the second component is a glass-ceramic substrate having I/O pads and the interposer is joined to the substrate by co-sintering using the substrate I/O pads and the interposer I/O pads to provide a glass-ceramic pin grid array.