Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure

• US 6,320,203 B1
• Filed: 02/12/1999
• Issued: 11/20/2001
• Est. Priority Date: 07/28/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US09/249,962
• Time in Patent Office: 1,012 Days
• Field of Search: 257/69, 257/928, 257/66, 257/354, 257/351
• US Class Current: 257/69
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: Y10S 257/928 with shorted PN or schottky junction other than emitter junction

Abstract

A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers wherein a first doped and activated polysilicon layer (either n-type and p-type) is patterned on a substrate. An isolation material layer is formed abutting the first doped and activated polysilicon layer in the corners formed at the junction between the first doped and activated polysilicon layer and the substrate. A second doped and activated polysilicon layer (either n-type or p-type) is applied over the first doped and activated polysilicon layer and the isolation material layer. The second doped and activated polysilicon layer is planarized to the height of the first doped and activated polysilicon layer. The first and second doped and activated polysilicon layers are etched to substantially bifurcate the first and second doped and activated polysilicon layers. Further processing steps known in the art are utilized to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in present methods.

Claims

1. A MOS structure, comprising:

at least two first activated areas of a first conductivity type, adjacent activated areas of said first conductivity type being laterally spaced apart from one another to facilitate at least partial positioning of a transistor gate structure laterally therebetween;

at least two second activated areas of a second conductivity type, said second conductivity type being opposite said first conductivity type;

at least one isolation barrier comprising a dielectric material, said at least one isolation barrier located between at least one first activated area and at least one second activated area, said at least one isolation barrier having at most the same height as said at least one second activated area; and

at least one conductive plug with a single downwardly extending member contacting a first activated area, a second activated area, and an isolation barrier located between said first and second activated areas.

2. The MOS structure of claim 1, wherein said at least two first activated areas each comprise doped polysilicon.

3. The MOS structure of claim 2, wherein said doped polysilicon comprises an n-type dopant.

4. The MOS structure of claim 2, wherein said doped polysilicon comprises a p-type dopant.

5. The MOS structure of claim 2, wherein said at least two second activated areas each comprise doped polysilicon.

6. The MOS structure of claim 5, wherein said doped polysilicon of said at least two second activated areas comprises a dopant with a conductivity type opposite that of said at least two first activated areas.