Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same

• US 6,320,213 B1
• Filed: 12/19/1997
• Issued: 11/20/2001
• Est. Priority Date: 12/19/1997
• Status: Expired due to Term

• Current Assignee: Entegris Incorporated
• Original Assignee: Advanced Technology Materials, Inc. (Entegris Incorporated)
• Inventors: Kirlin, Peter S., McIntryre, Paul, Summerfelt, Scott R.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Cao, Phat X.
• Application Number:
  US08/994,089
• Time in Patent Office: 1,432 Days
• Field of Search: 257/295, 257/296, 257/763, 257/753, 257/764, 257/303, 257/306
• US Class Current: 257/295
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

A dynamic random access memory device (100) includes storage capacitors using a high dielectric constant material, such as, BaSrTiO₃, SrBi₂Ta₂O₉ and PbZrTiO₃, for the capacitors'"'"' insulator. The device includes a conductive plug (106) formed over and connecting with a semiconductor substrate (102). A buffer layer (107) of titanium silicide lays over the plug, and this layer serves to trap “dangling” bonds and to passivate the underlying surface. A first diffusion barrier layer (108), e.g., titanium aluminum nitride, covers the titanium silicide. A capacitor first electrode (110) lays over the diffusion barrier layer. The high dielectric constant material (112) is laid over the capacitor first electrode. A capacitor second electrode (116) is laid over the high dielectric constant material. A second diffusion barrier layer (120) is deposited on the capacitor second electrode. A conductor, such as aluminum (130), is laid over the second diffusion barrier layer. An isolation dielectric (132) can be deposited over the conductor at a high temperature without causing oxygen or metallic diffusion through the first and second diffusion barrier layers.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a conductive plug formed over the substrate;

a buffet layer formed on the plug;

a first diffusion barrier layer covering the entire buffer layer;

a first capacitor electrode laid over the first diffusion barrier layer, wherein the diffusion barrier layer isolates the electrode from underlying layers;

a layer of high dielectric constant material laid over the first capacitor electrode;

a second capacitor electrode laid over the high dielectric constant material;

a second diffusion barrier layer laid over the second capacitor electrode; and

a conductor connecting with the second diffusion barrier layer, wherein the first and second diffusion barrier layers are conductive and independently comprise materials selected from the group consisting of;

(a) amorphous nitrides selected from the group consisting of;

TiSiN, TaBN, IiBN, and TaSiN,

(b) exotic conductive nitrides selected from the group consisting of;

TiAlN, Hfn, YN, ScN, LaN, rare earth nitrides, N-deficient AlN, doped AlN, MgN, CaN, SrN, BaN, and alloys thereof with an alloying component selected from the group consisting of Ti, Ga, Ni, Co, Ta and W, and

(c) noble-metal-insulator-alloys selected from the group consisting of PdSiN, PtSiN, PtSiO, PdSiO, PdBO, PdBN, PdAlO, PdAIN, RuSiO, RuSiN, IrSiO, IrSiN, ReSiO, ReSiN, RhAlO, AuSiN and AgSiN.

2. A semiconductor device, in accordance with claim 1, wherein:

the conductor is a metal.

3. A semiconductor device, in accordance with claim 1, wherein:

the conductor is a material selected from a group of materials including aluminum, aluminum alloys, tungsten, tungsten alloys, copper and copper alloys.

4. A semiconductor device, in accordance with claim 11, wherein:

the first and second diffusion barrier layers independently comprise materials selected from the group consisting of TiSiN, TiAlN and PdSiN.

5. A semiconductor device, in accordance with claim 11, wherein:

the first and second diffusion barrier layers each comprise TiAlN.

6. A semiconductor device, in accordance with claim 1, wherein:

the first and second capacitor electrodes are metallic materials.

7. A semiconductor device, in accordance with claim 1, wherein:

the first and second capacitor electrodes are metallic materials selected from a group of materials including aluminum group metals, tungsten group metals, platinum group metals, palladium group metals, ruthenium group metals, iridium group metals, rhenium group metals, rhodium group metals, gold group metals, silver group metals, copper group metals, conductive metal compounds, conductive perovskite like materials, reactive metals, doped silicon, and doped germanium.

8. A semiconductor device, in accordance with claim 1, wherein:

the high dielectric constant material is a perovskite material.

9. A semiconductor device, in accordance with claim 8, wherein:

the high dielectric constant material is a complex metal oxide.

10. A semiconductor device, in accordance with claim 1, wherein:

the high dielectric constant material is selected from a group of materials including perovskites, pyroelectrics, ferroelectrics, high-dielectric-constant-oxides, (Ba, Sr, Ca, Mg) (Ti,Zr)o₃, (Pb,La)(Zr,Ti)o₃, SrBi₂Ta₂O₉ bismuth titanate, potassium tantalate, lead scandium tantalate, lead niobate, potassium niobate, lead zinc niobate, lead magnesium niobate, tantalum pentoxide, and yttrium oxide.

11. A semiconductor device, in accordance with claim 1, wherein:

the conductive plug is a material selected from a group of materials including polysilicon, doped silicon, aluminum, aluminum alloys, tungsten, tungsten alloys, copper and copper alloys.

12. A semiconductor device, in accordance with claim 1, wherein:

the buffer layer is titanium silicide.

13. A semiconductor device, in accordance with claim 1, further comprising:

an interlevel dielectric layer deposited over the diffusion barrier layer.