SOI CMOS body contact through gate, self-aligned to source- drain diffusions

• US 6,320,225 B1
• Filed: 07/13/1999
• Issued: 11/20/2001
• Est. Priority Date: 07/13/1999
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Hargrove, Michael J., Mandelman, Jack A.
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US09/351,647
• Time in Patent Office: 861 Days
• Field of Search: 257/347, 257/412, 257/773, 257/900, 257/413, 257/401
• US Class Current: 257/347
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and process for making a semiconductor device with SOI body contacts under the gate conductor. The gate conductor is partitioned into segments and provides a body contact under each gate conductor segment over the width of the device. A plurality of body contacts may be distributed across the length of the gate conductor. This results in a relatively short path for holes leaving the body to traverse and allows accumulated charge to be removed from the body region under the gate. The structure provides for stable and efficient body-contact operation for SOI MOSFETS of any width operating at high speeds.

Claims

1. A body contact structure under a gate conductor on a silicon on insulator substrate comprising:

(a) a first insulating layer overlying said gate conductor and said silicon on insulator substrate;

(b) an opening in said substrate extending from a top surface of said first insulating layer through said gate conductor to a semiconductor substrate, said opening having a pair of sidewalls and a bottom;

(c) an insulating spacer, one on each of said sidewalls of said opening adjacent said first insulating layer and said gate conductor;

(d) a layer of a first conductive material in said opening;

(e) a layer of a second insulating material over said first conductive material layer.

2. The structure of claim 1 further comprising:

(f) a layer of a second conductive material over said second insulating layer.

3. The structure of claim 2 further comprising a salicide over said gate conductor.

4. The structure of claim 1 wherein a dopant is implanted into said semiconductor substrate at the bottom of said opening.

5. The structure of claim 4 wherein said dopant is boron.

6. The structure of claim 1 wherein said first and second insulating layers are tetraethoxysilane.

7. The structure of claim 1 wherein said insulating spacer is silicon nitride.

8. The structure of claim 1 wherein said first conductive material is P+ polysilicon.

9. The structure of claim 2 wherein said second conductive material is polysilicon.