Heterogeneous CPLD logic blocks

• US 6,320,410 B1
• Filed: 03/15/2000
• Issued: 11/20/2001
• Est. Priority Date: 03/17/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Jones, Christopher W., Malhotra, Vinod
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tran, V.
• Application Number:
  US09/525,955
• Time in Patent Office: 615 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programmable logic device comprising a first plurality of logic blocks each comprising a first number of I/O macrocells, a second plurality of logic blocks each comprising a second number of I/O macrocells and a configuration circuit configured to enable one or more of said first plurality of logic blocks and/or one or more of said second plurality of logic blocks.

Claims

1. A programmable logic device comprising:

a first plurality of logic blocks each comprising a first number of I/O macrocells;

a second plurality of logic blocks each comprising a second number of I/O macrocells; and

a configuration circuit configured to enable one or more of said first plurality of logic blocks and/or one or more of said second plurality of logic blocks, wherein said first number is equal to a positive integer and said second number is zero.

2. The programmable logic device according to claim 1, wherein one or more of said logic blocks are heterogeneous.

3. The programmable logic device according to claim 1, wherein said one or more of logic blocks have no I/O macrocells.

4. The programmable logic device according to claim 3, wherein said device has no programmable routing between said macrocells and one or more of said I/O pins.

5. The programmable logic device according to claim 4, wherein one or more of said logic blocks have zero I/O macrocells, wherein said logic blocks with zero I/O macrocells allow production of a lower density device by disabling some or all of the logic blocks.

6. The programmable logic device according to claim 5, wherein said device is configured to allow migration of a design to a different density while keeping the same footprint.

7. The programmable logic device according to claim 6, wherein one or more groups of said devices have a different number densities, wherein each group is sorted with a single probe card.

8. The programmable logic device according to claim 1, wherein a first set of one or more of said logic blocks have a positive number of I/O macrocells and a second set of one or more of said logic blocks have zero I/O macrocells, wherein said first and second sets of logic blocks are in the same physical logic blocks.

9. A method for configuring a programmable logic device having a first plurality of logic blocks comprising a first number of I/O macrocells and a second plurality of logic blocks comprising a second number of I/O macrocells, comprising the steps of:

(A) enabling one or more of said first plurality of logic blocks; and

(B) enabling one or more of said second plurality of logic blocks, wherein said first number is equal to a positive integer and said second number is zero.

10. The method according to claim 9, wherein one or more of said logic blocks are heterogeneous.

11. The method according to claim 9, wherein one or more of said logic blocks have zero I/O macrocells, wherein said logic blocks with zero I/O macrocells allow production of a lower density device by disabling some or all of the logic blocks.

12. The method according to claim 11, wherein said method allows one or more different densities of logic devices to be included in a single base design.

13. The method according to claim 12, wherein said one or more different densities have a similar bonding diagram.

14. The method according to claim 13 further comprising the step of:

sorting said different densities using a single probe card.

15. The method according to claim 9, wherein a first set of one or more of said logic blocks have a positive number of I/O macrocells and a second set of one or more of said logic blocks have zero I/O macrocells, wherein said first and second sets of logic blocks are in the same physical logic blocks.

16. A method of defining two densities of programmable logic devices that have the same total number of I/O macrocells comprising the following steps:

(A) assigning a number N1 to be the number of macrocells in the larger density device;

(B) assigning a number M1 to be the number of macrocells in the smaller density device;

(C) declaring a number J to be the number of macrocells in a logic block;

(D) declaring a number K to be the total number of I/O macrocells in each device;

(E) declaring a number N2 to be the quotient of the number N1 divided by the number J;

(F) declaring a number M2 to be the quotient of the number M1 divided by the number J;

(G) declaring a number M3 to be the quotient of the number K divided by the number M2;

(H) declaring a number M4 to be the difference between the number J and the number M3;

(I) declaring a number N5 to be the difference between the number N2 and the number M2;

(J) assigning a first density device to have a number of logic blocks equal to M2, each with a number of I/O macrocells equal to M3 and a number of buried macrocells equal to M4; and

(K) assigning a second density device to have a number of logic blocks equal to N5, each with a number of buried macrocells equal to J, and a number of logic blocks equal to M2, each with a number of I/O macrocells equal to M3 and a number of buried macrocells equal to M4.

17. A programmable logic device comprising a plurality of logic blocks having the same number of macrocells, wherein at least two of said plurality of logic blocks have a different number of I/O macrocells, at least one of said plurality of logic blocks has an I/O macrocell and at least one of said plurality of logic blocks does not have an I/O macrocell.