High-speed, low-power continuous-time CMOS current comparator
First Claim
1. A current comparator, comprising:
- a CMOS complementary amplifier to receive an input current from an input node and generate correspondingly output voltage at an output node, comprising;
a NMOS and a PMOS connected in series, the NMOS and the PMOS having control gates that connect to form the input node, the NMOS and the PMOS having drain electrodes coupled to the output node; and
a resistive feedback circuit connected between the input node and the output node; and
a secondary amplifier to receive the output voltage at the output node and output a corresponding rail-to-rail result signal.
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Abstract
A CMOS current comparator featuring shortened response delay times lower power consumption, smaller area and enhanced process robustness. The current comparator is comprised of a CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. The CMOS complementary amplifier receives an input current from an input node which generates an output voltage at a corresponding output node. The CMOS complementary amplifier is comprised of an N-type metal oxide semiconductor field effect transistor (NMOS) and a P-type metal oxide semiconductor field effect transistor (PMOS) connected in series. Control gates on both the NMOS and PMOS are connected to form the input node. NMOS and PMOS drain electrodes are also coupled to the output node. The CMOS complementary amplifier further has a resistive feedback circuit which is connected between the input and output nodes. The two resistive-load amplifiers are connected in cascade form to receive and amplify output voltage from the CMOS complementary amplifier. The result being a correspondingly output of amplified voltage. The two CMOS inverters are also connected in cascade form to receive the amplified voltage and output corresponding rail-to-rail result signal.
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Citations
20 Claims
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1. A current comparator, comprising:
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a CMOS complementary amplifier to receive an input current from an input node and generate correspondingly output voltage at an output node, comprising;
a NMOS and a PMOS connected in series, the NMOS and the PMOS having control gates that connect to form the input node, the NMOS and the PMOS having drain electrodes coupled to the output node; and
a resistive feedback circuit connected between the input node and the output node; and
a secondary amplifier to receive the output voltage at the output node and output a corresponding rail-to-rail result signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
a small-signal amplifier to receive and amplify the output voltage from the CMOS complementary amplifier and output an amplified voltage; and
a full-ranged amplifier to receive the amplified voltage and output the rail-to-rail result signal.
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8. The current comparator as claimed in claim 7, wherein the small-signal amplifier comprises two resistive-load amplifiers connected in cascade form.
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9. The current comparator as claimed in claim 8, wherein each of the resistive-load amplifiers has a MOS transistor and a load resistor connected in series.
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10. The current comparator as claimed in claim 7, wherein the full-ranged amplifier comprises two CMOS inverters connected in cascade form.
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11. The current comparator as claimed in claim 1, wherein the resistive feedback circuit is used to decrease the input and output resistances of the CMOS complimentary amplifier, so that speed of the current comparator can be increased.
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12. The current comparator as claimed in claim 1, wherein the current comparator is a continuous-time current comparator and the input current is continuous.
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13. The current comparator as claimed in claim 2, wherein the two current-suppressing resistors are used to reduce the working current through the NMOS and the PMOS;
- and when the input current is zero, size of the two current-suppressing resistors can be adjusted to control the output voltage.
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14. The current comparator as claimed in claim 8, wherein the resistive-load amplifiers are used to provide additional gain for the current comparator in that when the magnitude of the input current increases, power consumption of the current comparator will not be limited by bias current.
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15. A current comparator, comprising:
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a CMOS complementary amplifier to receive an input current from an input node and generate corresponding output voltage at an output node, comprising;
a NMOS and a PMOS connected in series, the NMOS and the PMOS having control gates that connect to form the input node, the NMOS and the PMOS having drain electrodes coupled to the output node; and
a resistive feedback circuit connected between the input node and the output node;
two resistive-load amplifiers connected in cascade form to receive and amplify the output voltage from the CMOS complementary amplifier and output corresponding amplified voltage; and
two CMOS inverters connected in cascades form to receive the amplified voltage and output a corresponding rail-to-rail result signal. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification
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- Resources
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Current AssigneeWinbond Electronics Corporation
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Original AssigneeWinbond Electronics Corporation
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InventorsShi, Bingxue, Chen, Lu
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Primary Examiner(s)Callahan, Timothy P.
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Assistant Examiner(s)Luu, An T.
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Application NumberUS09/689,567Time in Patent Office405 DaysField of Search327/77, 327/80, 327/108, 327/109, 327/112, 326/82, 326/83, 326/84, 326/85, 326/86, 326/87, 326/91, 330/262, 330/264, 330/265US Class Current327/77CPC Class CodesH03K 5/086 generated by feedbackH03K 5/2472 using field effect transist...
