DAC driver circuit with pixel resetting means and color electro-optic display device and system incorporating same
First Claim
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1. A driver circuit for an electro-optic display device comprising an active row-and-column matrix array of pixels, the driver circuit comprising:
- a control circuit for sequentially addressing the pixels of the device with analog display signals, the control circuit comprising selection means for selecting a row of pixels during a row selection period, and writing means for applying the analog signals to the selected pixels over one or more columns during the row selection period;
a DAC for converting a stream of incoming digital display signals into the analog display signals, the DAC including a ramp generator for generating an analog ramp down from a high value to a low value during the row selection period, and sample-and-hold means for selecting an analog signal from the ramp corresponding to the sampled digital signal, and holding the analog signal for application to the selected pixels;
characterized in that the selection means of the control circuit is set to simultaneously with the selecting a row of pixels during a row selection period, selecting pixels to be reset to a pre-determined state prior to writing, and the writing means is set to apply a resetting pulse from the analog ramp generator to the selected pixels prior to selection of the analog information signals from the DAC, whereby the artifacts caused by the residual state of the electro-optic material are reduced or eliminated.
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Abstract
In a digital-to-analog (DAC) driver circuit for a color electro-optic display device employing a global ramp generator, color artifacts caused by the residual state of the electro-optic material of the pixels from previously addressed data signals are substantially reduced or eliminated by providing a resetting pulse from the ramp generator to selected pixels prior to addressing with the next set of data signals.
67 Citations
11 Claims
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1. A driver circuit for an electro-optic display device comprising an active row-and-column matrix array of pixels, the driver circuit comprising:
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a control circuit for sequentially addressing the pixels of the device with analog display signals, the control circuit comprising selection means for selecting a row of pixels during a row selection period, and writing means for applying the analog signals to the selected pixels over one or more columns during the row selection period;
a DAC for converting a stream of incoming digital display signals into the analog display signals, the DAC including a ramp generator for generating an analog ramp down from a high value to a low value during the row selection period, and sample-and-hold means for selecting an analog signal from the ramp corresponding to the sampled digital signal, and holding the analog signal for application to the selected pixels;
characterized in that the selection means of the control circuit is set to simultaneously with the selecting a row of pixels during a row selection period, selecting pixels to be reset to a pre-determined state prior to writing, and the writing means is set to apply a resetting pulse from the analog ramp generator to the selected pixels prior to selection of the analog information signals from the DAC, whereby the artifacts caused by the residual state of the electro-optic material are reduced or eliminated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification
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Current AssigneePhilips Electronics North America Corporation (Koninklijke Philips N.V.)
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Original AssigneePhilips Electronics North America Corporation (Koninklijke Philips N.V.)
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InventorsAlbu, Lucian Remus, Janssen, Peter J.
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Primary Examiner(s)WU, XIAO MIN
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Application NumberUS09/375,952Time in Patent Office826 DaysField of Search345/87, 345/88, 345/89, 345/98, 345/99, 345/100, 345/95, 345/96, 345/97, 345/94, 345/208, 345/209, 345/210US Class Current345/98CPC Class CodesG09G 2310/0235 Field-sequential colour dis...G09G 2310/0251 Precharge or discharge of p...G09G 2310/0259 with use of an analog or di...G09G 2310/027 Details of drivers for data...G09G 2310/066 Waveforms comprising a gent...G09G 2320/02 Improving the quality of di...G09G 3/2011 by amplitude modulationG09G 3/3648 using an active matrix G09G...G09G 3/3677 suitable for active matrice...G09G 3/3688 suitable for active matrice...H04N 2005/745 Control circuits thereforH04N 5/7441 the modulator being an arra...
