Driving circuit for liquid crystal display in dot inversion method

• US 6,320,566 B1
• Filed: 03/27/1998
• Issued: 11/20/2001
• Est. Priority Date: 04/30/1997
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Go, Yong Suk
• Primary Examiner(s): Saras, Steven
• Assistant Examiner(s): KUMAR, SRILAKSHMI K
• Application Number:
  US09/049,469
• Time in Patent Office: 1,334 Days
• Field of Search: 345/89-100, 349/149, 327/269
• US Class Current: 345/99
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

The present invention provides a driving circuit for providing display signals to a liquid crystal display panel through a plurality of data lines. The driving circuit includes a clock signal generator producing a first clock signal and a second clock signal, a phase of the first clock signal being 180-degrees from that of a phase of the second clock signal; and a data driver to be connected to the plurality of data lines through one side of the liquid crystal display panel, the data driver including a latch circuit having a plurality of output terminals each to be connected to the respective one of the data lines through a respective XOR gate, respective XOR gates connected to the odd data lines receiving the first clock signal to output first pixel driving signals having a predetermined polarity to the respective odd data lines, respective XOR gates connected to the even data lines receiving the second clock signal to output second pixel driving signals having a reverse polarity relative to the first video signals to the respective even data lines.

Claims

1. A liquid crystal display device, comprising:

a first substrate including a plurality of odd data lines and even data lines and a plurality of scan lines, the plurality of odd and even data lines being substantially perpendicular to the plurality of scan lines;

a second substrate opposite the first substrate, the second substrate including a plurality of odd-numbered common electrodes and even-numbered common electrodes disposed substantially in parallel with the plurality of odd and even data lines, respectively;

a clock signal generator producing a first clock signal and a second clock signal, a phase of the first clock signal being 180-degrees from that of a phase of the second clock signal;

a common voltage generator applying a first common voltage to the odd-numbered common electrodes disposed on the second substrate, and a second common voltage to the even-numbered common electrodes disposed on the second substrate; and

a data driver connected to the plurality of data lines through one side of the first substrate, the data driver including a latch circuit having a plurality of output terminals each connected to a respective one of the data lines through a respective gate, respective gates connected to the odd data lines receiving the first clock signal to output first pixel driving signals having a predetermined polarity to the respective odd data lines, respective gates connected to the even data lines receiving the second clock signal to output second pixel driving signals having a reverse polarity relative to the first pixel driving signals to the respective even data lines.

2. The liquid crystal display device according to claim 1, wherein the clock signal generator generates digital signals as the first clock signal and the second clock signal.

3. The liquid crystal display device according to claim 1, wherein the data driver is formed on the first substrate.

4. A circuit for driving a liquid crystal display device with a video data, comprising:

a latch for latching the video data to output video signals through a plurality of output terminals, the plurality of output terminals being divided into a first group and a second group;

a clock signal generator producing a first clock signal and a second clock signal, the phase of the first clock signal being 180-degrees from that of the second clock signal;

a plurality of first logical gates each performing an exclusive OR operation with the first clock signal and the video signal from the first group of the output terminals of the latch to output an operated signal; and

a plurality of second logical gates each performing an exclusive OR operation with the second clock signal and the video signal from the second group of the output terminals of the latch to output an operated signal.

5. The circuit according to claim 4, wherein a plurality of data lines are consecutively numbered for identification purposes, and the first group of the data lines includes odd numbered data lines, and the second group of data lines includes even numbered data lines.

6. A liquid crystal display device, comprising:

a first substrate including;

a plurality of data lines separated as odd data lines and even data lines,

a plurality of scan lines substantially perpendicular to the plurality of data lines,

a plurality of pixel electrodes each disposed at areas surrounded by the scan lines and data lines, and

a plurality of thin film transistors each disposed at a respective intersection of the data lines and the scan lines, a gate of each thin film transistor being connected to an adjacent scan line, a source of each thin film transistor being connected to an adjacent data line, and a drain of each thin film transistor being connected to an adjacent pixel electrode;

a second substrate opposite the first substrate, the second substrate including a plurality of odd common electrodes and even common electrodes disposed substantially in parallel with the plurality of data lines;

a liquid crystal material interposed between the first substrate and the second substrate;

a clock signal generator producing a first clock signal and a second clock signal, the phase of the first clock signal being 180-degrees from that of the second clock signal;

a common voltage generator applying a first common voltage to the odd common electrodes disposed on the second substrate, and applying a second common voltage to the even common electrodes disposed on the second substrate;

a data driver connected to the plurality of data lines through one side of the first substrate, the data driver including a latch circuit having a plurality of output terminals each connected to a respective one of the data lines through a respective gate, respective gates connected to the odd data lines receiving the first clock signal to output first pixel driving signals having a predetermined polarity to the respective odd data lines, respective gates connected to the even data lines receiving the second clock signal to output second pixel driving signals having a reverse polarity relative to the first pixel driving signals to the respective even data lines; and

a scan driver outputting scan signals to the plurality of scan lines on the first substrate to drive the thin film transistors connected thereto.

7. The liquid crystal display device according to claim 6, wherein the data driver is formed on the first substrate.

8. The liquid crystal display device according to claim 6, wherein the scan driver is formed on the first substrate.

9. A driving circuit for providing display signals to a liquid crystal display panel through a plurality of data lines being separated as odd data lines and even data lines, the driving circuit comprising:

a clock signal generator producing a first clock signal and a second clock signal, a phase of the first clock signal being 180-degrees from that of a phase of the second clock signal; and

a data driver to be connected to the plurality of data lines through one side of the liquid crystal display panel, the data driver including a latch circuit having a plurality of output terminals each to be connected to the respective one of the data lines through a respective gate, respective gates connected to the odd data lines receiving the first clock signal to output first pixel driving signals having a predetermined polarity to the respective odd data lines, respective gates connected to the even data lines receiving the second clock signal to output second pixel driving signals having a reverse polarity relative to the first pixel driving signals to the respective even data lines.