CMOS image sensor with reduced fixed pattern noise

• US 6,320,616 B1
• Filed: 06/02/1997
• Issued: 11/20/2001
• Est. Priority Date: 06/02/1997
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Sarnoff Corporation (SRI International, Inc.)
• Inventors: Sauer, Donald Jon
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): VU, NGOC YEN T
• Application Number:
  US08/867,653
• Time in Patent Office: 1,632 Days
• Field of Search: H04/N.5217, H04/N.964, H04/N.314, 250/208.1, 348/207, 348/241-250, 348/294, 348/310, 348/311, 348/312
• US Class Current: 348/241
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

Abstract

A correlated double-sampling circuit for sampling an input signal received from a pixel sensor circuit via an input line. According to one embodiment, a first switch selectively couples a junction of first terminals of a first capacitor and a second capacitor to the input line. A second switch selectively couples an output node coupled to a second terminal of the second capacitor to a reference voltage. A third switch selectively couples the output node to an output line.

Claims

1. A correlated double-sampling circuit for sampling an input signal received via an input line, the circuit comprising:

a first switch which selectively couples (a) a junction of first terminals of a first capacitor and a second capacitor to (b) the input line,

a second switch which selectively couples (c) an output node at a second terminal of the second capacitor to (d) a reference voltage, and

a third switch which selectively conductively couples the output node to an output line.

2. The circuit of claim 1, wherein the first switch comprises a first transistor, the second switch comprises a second transistor, and the third switch comprises a third transistor, wherein the gate terminal of the first transistor is coupled to a sample and hold signal, the gate terminal of the second transistor is coupled to a clamp signal, and the gate terminal of the third transistor is coupled to a column select signal.

3. The circuit of claim 2, wherein:

the sample and hold signal, the clamp signal, and the column select signal are applied to that;

an initial input signal is applied to the junction and the reference voltage to the output node during an initial time period to provide a voltage across the second capacitor representative of the difference between the initial input signal and the reference voltage;

the output node is isolated from the reference voltage during a second time period so that the voltage at the output node changes in response to a change in the input signal; and

the junction is isolated from the input line during a third time period so that the voltage at the output node is represented as a net signal charge stored across the series combination of the first and second capacitors.

4. The circuit of claim 3, wherein the output line has an output line capacitance and is coupled to the reference voltage via a fourth switch to initially apply the reference voltage to the output line and to isolate the output line from the reference voltage thereafter.

5. The circuit of claim 4, wherein the sample and hold signal, the clamp signal, and the column select signal are applied so that, after the junction is isolated from the input line and the output line is isolated from the reference voltage, the output node is coupled to the output line to cause the voltage on the output line to change by an amount related to the change in the input signal.

6. The circuit of claim 4, wherein the capacitance of the series connection of the first and second capacitors is approximately equal to the output line capacitance.

7. The circuit of claim 1, wherein the output line has an output line capacitance and is coupled to the reference voltage via a fourth switch to apply the reference voltage to the output line.

8. The circuit of claim 7, wherein the output line capacitance comprises a parasitic capacitance of the output line.

9. The circuit of claim 1, wherein the second terminal of the first capacitor is coupled to ground.

10. The circuit of claim 1, wherein the input signal is received from a pixel sensor circuit via the input line.

11. A correlated double-sampling circuit for sampling an input signal received via an input line, comprising:

(a) a capacitor coupled at a first terminal to the input line and coupled at a second terminal to an output node;

(b) means for applying an initial voltage across the capacitor representative of the difference between an initial input signal and a reference voltage and for applying the reference voltage to the output node during an initial time period;

(c) means for isolating the output node from the reference voltage during a second time period; and

(d) means for coupling a change in the input signal to the first terminal of the capacitor, wherein the voltage at the output node changes in response to the change in the input signal.

12. The circuit of claim 11, further comprising (e) means for isolating the first terminal of the capacitor from the input line during a third time period.

13. The circuit of claim 11, further comprising a second capacitor coupled between the first terminal of the capacitor and ground.

14. The circuit of claim 11, wherein the input signal is received from a pixel sensor circuit via the input line.

15. The circuit of claim 11, wherein means (a)-(c) comprise first, second, and third transistors coupled to the capacitor.

16. The circuit of claim 11, wherein the first transistor selectively couples the first terminal of the capacitors to the input line, the second switch selectively couples the output node to the reference voltage, and the third switch selectively couples the output node to an output line.

17. The circuit of claim 16, wherein the gate terminal of the first transistor is coupled to a sample and hold signal, the gate terminal of the second transistor is coupled to a clamp signal, and the gate terminal of the third transistor is coupled to a column select signal, wherein the sample and hold signal, the clamp signal, and the column select signal are applied to cause the functions of means (b)-(d) to be implemented.

18. The circuit of claim 16, wherein the output line has an output line capacitance and is coupled to the reference voltage via a fourth transistor to initially apply the reference voltage to the output line and to isolate the output line from the reference voltage thereafter.

19. The circuit of claim 18, further comprising:

means for isolating the first terminal of the capacitor from the input line during a third time period; and

means for coupling the output node, after the first terminal of the capacitor is isolated from the input line and the output line is isolated from the reference voltage, to the output line to cause the voltage on the output line to change by an amount related to the change in the input signal.