Electronic package

• US 6,320,757 B1
• Filed: 07/12/2000
• Issued: 11/20/2001
• Est. Priority Date: 07/12/2000
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liu, Sheng-Tsung
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US09/614,684
• Time in Patent Office: 496 Days
• Field of Search: 361/734, 361/738, 361/760, 361/763, 361/767, 361/777, 361/780, 361/782, 361/783, 361/818, 257/668, 257/691, 257/723, 257/724, 257/784, 257/786
• US Class Current: 361/760
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48233 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01031 Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

An electronic package comprises a chip disposed on the upper surface of a substrate. The upper surface of the substrate is provided with a ground ring, a power ring, and a plurality of conductive traces arranged at the periphery of the ground ring and the power ring. The electronic package comprises at least a surface-mountable device connected across the ground ring and the power ring. The present invention is characterized in that the surface-mountable device has at least a bonding region formed on one end contact thereof for bonding to a bonding wire thereby allowing the chip to be electrically connected to the ground ring or power ring directly through the end contact of the surface-mountable device.

Claims

1. An electronic package comprising:

a substrate having opposing upper and lower surfaces, the upper surface of the substrate being provided with a ground ring, a power ring, and a plurality of conductive traces arranged at the periphery of the ground ring and the power ring;

at least a surface-mountable device connected across the ground ring and the power ring, the surface-mountable device comprising two end contacts and at least a bonding region formed on one of the end contacts;

a chip disposed on the upper surface of the substrate, the chip having a plurality of bonding pads located about the periphery thereof; and

at least a first bonding wire having one end connected to one of the bonding pads of the chip and the other end connected to the bonding region of the surface-mountable device.

2. The electronic package as claimed in claim 1, wherein the bonding region of the surface-mountable device comprises a layer of metal selected from the group consisting of gold and palladium covering the end contact of the surface-mountable device.

3. The electronic package as claimed in claim 1, wherein the bonding region of the surface-mountable device comprises a layer of nickel covering the end contact of the surface-mountable device, and a layer of metal selected from the group consisting of gold and palladium covering the nickel layer.

4. The electronic package as claimed in claim 1, wherein the bonding region of the surface-mountable device comprises a layer of nickel covering the end contact of the surface-mountable device, a layer of palladium covering the nickel layer, and a layer of gold covering the palladium layer.

5. The electronic package as claimed in claim 1, wherein the surface-mountable device is a capacitor.

6. The electronic package as claimed in claim 1, further comprising a plurality of second bonding wires electrically connecting the bonding pads of the chip to the power ring, the ground ring and corresponding conductive traces of the substrate, respectively.