Programmable impedance device

• US 6,320,788 B1
• Filed: 09/11/2000
• Issued: 11/20/2001
• Est. Priority Date: 09/25/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Corporation (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Sansbury, James D., Wang, Sau C.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/658,963
• Time in Patent Office: 435 Days
• Field of Search: 365/185.01, 365/185.05, 365/185.19, 365/185.1, 365/185.03, 365/185.08
• US Class Current: 365/185.1
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates

Abstract

A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.

Claims

1. A circuit comprising:

a first impedance device connected between a first voltage level and a node;

a second impedance device connected between the node and a second voltage level, wherein one of the impedance devices comprises a non-volatile programmable impedance element having an impedance value selectable by configuring a floating gate.

2. The circuit of claim 1, wherein the non-volatile programmable impedance element comprises:

a memory cell comprising the floating gate, wherein the memory cell is configurable to have more than two threshold voltages; and

a programmable impedance device sharing the floating gate, wherein the impedance value is based on a threshold value of the memory cell.

3. The circuit of claim 2, wherein threshold voltages of the memory cell is adjusted by a number of pulses of a programming voltage applied at a control gate of the memory cell.

4. The circuit of claim 1, wherein the circuit is a voltage bias generator, the bias voltage value being supplied at the node.

5. A method of providing a delay, comprising:

applying a programming voltage to a floating gate memory device;

configuring the floating gate memory device to have a programmed threshold voltage that is a value between a first threshold value and a second threshold voltage, inclusive; and

obtaining an impedance value for a delay network, coupled to the floating gate memory device, based on the threshold voltage of the floating gate memory device, wherein the delay network comprises;

a nonvolatile programmable impedance element coupled between an input node and an output node and having said impedance value; and

a capacitance coupled between the output node and a reference potential, wherein the circuit provides the delay based said impedance value.

6. The method of claim 5, wherein the capacitor is implemented using parasitic capacitance.

7. The method of claim 5, wherein a floating gate is shared between the floating gate memory device and the impedance element.

8. A programmable impedance element comprising:

a memory cell comprising a floating gate and a control gate configurable to have a plurality of threshold voltages; and

a programmable impedance device comprising a control gate and sharing the floating gate, wherein an impedance of the programmable impedance device is based on a threshold value of the memory cell.

9. The programmable impedance element of claim 8, wherein the floating gate of the memory cell and the floating gate of the programmable impedance device are connected.

10. The programmable impedance element of claim 8, wherein the floating gate of the memory cell and the floating gate of the programmable impedance device are independent.

11. The programmable impedance element of claim 8, wherein the floating gate of the memory cell is adjusted by a number of pulses of a programming voltage at a control gate of the memory cell.

12. The programmable impedance element of claim 8, wherein the floating gate of the memory cell is adjusted by a series of programming and erase operations using a binary-search-type algorithm.