Low voltage level power-up detection circuit

• US 6,320,809 B1
• Filed: 07/05/2000
• Issued: 11/20/2001
• Est. Priority Date: 07/05/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Raad, George B.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/610,373
• Time in Patent Office: 503 Days
• Field of Search: 365/226, 365/225.7, 327/143, 327/198, 327/270
• US Class Current: 365/226
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A low voltage power-up detection circuit for use includes a programmable resistance biasing network which provides an adjustable voltage to vary a power-up voltage detection point. The programming of the bias network can be set during testing of the device. The low voltage power-up detection circuit may be used with many devices including memory devices such as DRAMs.

Claims

1. A power-up detection circuit comprising:

a transistor for providing a voltage output signal when a first voltage is applied to a supply terminal, said transistor having a gate for receiving a second voltage generated from said first voltage; and

a biasing circuit for applying said second voltage to said gate, said biasing circuit being connected to receive said first voltage from said terminal and including a resistance circuit for dividing said first voltage applied to said terminal to produce said second voltage;

wherein said resistance circuit is variable for providing different voltage levels for said second voltage.

2. A circuit as in claim 1 wherein said resistance circuit comprises a programmable resistance network.

3. A circuit as in claim 2 wherein said programmable resistance network comprises a plurality of connected resistors and a plurality of transistor switches, said transistor switches being selectively operated to alter which of said resistors are electrically operable in said resistance network to thereby change said second voltage.

4. A circuit as in claim 3 wherein said plurality of resistors are connected in series and said transistor switches are respectively associated with said resistors such that when a transistor switch is turned on a respective resistor is shunted.

5. A circuit as in claim 3 further comprising a plurality of programmable elements respectively associated with said transistor switches, a transistor switch being rendered operative not depending on the programmed state of a respective programmable element.

6. A circuit as in claim 5 wherein said programmable elements are fuses connected between a third voltage and a gate of a respective transistor switch.

7. A circuit as in claim 5 wherein said programmable elements are anti-fuses connected between a third voltage and a gate of a respective transistor switch.

8. A circuit as in claim 6 or 7 wherein said third voltage is derived from said first voltage.

9. A circuit as in claim 1 further comprising an amplifier having at least one input connected to receive said voltage output signal and for providing a power-up detection output signal.

10. A circuit as in claim 9 wherein said amplifier is a differential amplifier and at least one input of said differential amplifier is connected to receive said voltage output signal.

11. A circuit as in claim 10 wherein said differential amplifier has one input connected to receive said voltage output signal and another input connected to receive a voltage taken from a gate of said transistor.

12. A memory device comprising:

a memory circuit including a memory array and an access circuit for reading data from and writing data into said array; and

a memory circuit power-up detection circuit comprising;

a transistor for providing a voltage output signal when a first voltage is applied to a supply terminal, said transistor having a gate for receiving a second voltage generated from said first voltage; and

a biasing circuit for applying said second voltage to said gate, said biasing circuit being connected to receive said first voltage from said terminal and including a resistance circuit for dividing said first voltage applied to said terminal to produce said second voltage;

wherein said resistance circuit is variable for providing different voltage levels for said second voltage.

13. A memory device as in claim 12 wherein said resistance circuit comprises a programmable resistance network.

14. A memory device as in claim 13 wherein said programmable resistance network comprises a plurality of connected resistors and a plurality of transistor switches, said transistor switches being selectively operated to alter which of said resistors are electrically operable in said resistance network to thereby change said second voltage.

15. A memory device as in claim 14 wherein said plurality of resistors are connected in series and said transistor switches are respectively associated with said resistors such that when a transistor switch is turned on a respective resistor is shunted.

16. A memory device as in claim 14 further comprising a plurality of programmable elements respectively associated with said transistor switches, a transistor switch being rendered operative not depending on the programmed state of a respective programmable element.

17. A memory device as in claim 16 wherein said programmable elements are fuses connected between a third voltage terminal and a gate of a respective transistor switch.

18. A memory device as in claim 16 wherein said programmable elements are anti-fuses connected between a third voltage and a gate of a respective transistor switch.

19. A memory device as in claim 17 or 18 wherein said third voltage is derived from said first voltage.

20. A memory device as in claim 12 further comprising an amplifier having at least one input connected to receive said voltage output signal and for providing a power-up detection output signal.

21. A memory device as in claim 20 wherein said amplifier is a differential amplifier and at least one input of said differential amplifier is connected to receive said voltage output signal.

22. A memory device as in claim 21 wherein said differential amplifier has one input connected to receive said voltage output signal and another input connected to receive a voltage taken from a gate of said transistor.

23. A processor system comprising:

a processor; and

a memory device coupled to said processor, said memory device comprising;

a memory circuit including a memory array and an access circuit for reading data from and writing data into said array; and

a memory circuit power-up detection circuit comprising;

a transistor for providing a voltage output signal when a first voltage is applied to a supply terminal, said transistor having a gate for receiving a second voltage generated from said first voltage; and

a biasing circuit for applying said second to voltage to said gate, said biasing circuit being connected to receive said first voltage from said terminal and including a resistance circuit for dividing said first voltage applied to said terminal to produce said second voltage;

wherein said resistance circuit is variable for providing different voltage levels for said second voltage.

24. A processor system as in claim 23 wherein said resistance circuit comprises a programmable resistance network.

25. A processor system as in claim 24 wherein said programmable resistance network comprises a plurality of connected resistors and a plurality of transistor switches, said transistor switches being selectively operated to alter which of said resistors are electrically operable in said resistance network to thereby change said second voltage.

26. A processor system as in claim 25 wherein said plurality of resistors are connected in series and said transistor switches are respectively associated with said resistors such that when a transistor switch is turned on a respective resistor is shunted.

27. A processor system as in claim 25 further comprising a plurality of programmable elements respectively associated with said transistor switches, a transistor switch being rendered operative not depending on the programmed state of a respective programmable element.

28. A processor system as in claim 27 wherein said programmable elements are fuses connected between a third voltage terminal and a gate of a respective transistor switch.

29. A processor system as in claim 27 wherein said programmable elements are anti-fuses connected between a third voltage terminal and a gate of a respective transistor switch.

30. A processor system as in claim 28 or 29 wherein said third voltage is derived from said first voltage.

31. A processor system as in claim 23 further comprising an amplifier having at least one input connected to receive said voltage output signal and for providing a power-up detection output signal.

32. A processor system as in claim 31 wherein said amplifier is a differential amplifier and at least one input of said differential amplifier is connected to receive said voltage output signal.

33. A processor system as in claim 32 wherein said differential amplifier has one input connected to receive said voltage output signal and another input connected to receive a voltage taken from a gate of said transistor.

34. A method of detecting a power-up condition of a circuit, said method comprising:

adjusting a resistance network which is coupled to a voltage supply terminal, which is adapted to receive a first voltage, to produce an adjusted second voltage from an applied said first voltage; and

using said adjusted second voltage to produce a signal indicating a power up condition;

wherein said adjusting further comprises setting a resistance value in an adjustable resistance network which divides said first voltage.

35. A method as in claim 34 wherein said setting comprises programming a resistance value for said resistance network.

36. A method as in claim 35 wherein said resistance network comprises a plurality of resistors and said programming determines which of said resistors are operative in said resistance network.

37. A method as in claim 36 wherein said programming permits one or more of said resistors to be selectively inoperative in said resistance network.

38. A method as in claim 36 wherein said adjusting occurs during a testing operation of said circuit.

39. A method of detecting a power-up condition of a memory device, said memory device having a power-up terminal for receiving a power-up indication signal, said method comprising:

operating a transistor to produce a voltage output signal when a first voltage is applied to a supply terminal, said transistor receiving second voltage at a gate terminal which is generated from said first voltage;

receiving said first voltage at a resistance divider circuit and producing said second voltage from said first voltage;

adjusting the resistance of said resistance divider circuit by setting a resistance value in an programmable resistance network to produce a predetermined value of said second voltage; and

using said voltage output signal to generate a power-up signal at said power-up terminal.