Semiconductor device reconciling different timing signals

• US 6,320,819 B2
• Filed: 12/12/2000
• Issued: 11/20/2001
• Est. Priority Date: 02/03/1998
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Tomita, Hiroyoshi, Kanda, Tatsuya
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/733,961
• Publication Number:
  US 20010000994A1
• Time in Patent Office: 343 Days
• Field of Search: 365/233, 365/189.05, 365/230.08, 365/194
• US Class Current: 365/233.11
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

Claims

1. A memory circuit, comprising:

an address-input circuit which latches address signals in response to a clock signal, and outputs the address signals in response to the clock signal, said address-input circuit includes a delay circuit which operates in response to the clock signal;

a data-input circuit which latches data signals in response to a strobe signal, and outputs the data signals in response to the clock signal;

an internal circuit which writes the data signals supplied from the data-input circuit in memory cells indicated by the address signals supplied from the address-input circuit; and

a bypass circuit provided in parallel to said delay circuit, wherein the address signals pass through the bypass circuit and bypass said delay circuit in a data-read mode.

2. The memory circuit as claimed in claim 1, said delay circuit comprising a shift-register.

3. The memory circuit as claimed in claim 1, said delay circuit receiving latched address signals latched by the address-input circuit.

4. The memory circuit as claimed in claim 3, said delay circuit delaying the latched address signals for 1.5 clock cycles.

5. A memory circuit, comprising:

an address-input circuit which latches address signals in response to a clock signal, and outputs the address signals in response to a strobe signal, the address-input circuit includes a delay circuit which operates in response to a clock signal;

a data-input circuit which latches data signals in response to a strobe signal, and outputs the data signals in response to the strobe signal;

an internal circuit which writes the data signals supplied from the data-input circuit in memory cells indicated by the address signals supplied from the address-input circuit; and

a bypass circuit provided in parallel to said delay circuit, wherein the address signals pass through the bypass circuit and bypass said delay circuit in a data-read mode.

6. The memory circuit as claimed in claim 5, said delay circuit comprising a shift-register.