System and method for data bus interface

• US 6,320,877 B1
• Filed: 03/10/2000
• Issued: 11/20/2001
• Est. Priority Date: 10/02/1997
• Status: Expired due to Term

• Current Assignee: Alcatel USA Sourcing L.P. (Nokia Corporation)
• Original Assignee: Alcatel USA Sourcing L.P. (Nokia Corporation)
• Inventors: Garcia, Jose A., Humphrey, Russell L., Vo, Long V.
• Primary Examiner(s): Patel, Ajit
• Assistant Examiner(s): Phunkulh, Bob A.
• Application Number:
  US09/522,661
• Time in Patent Office: 620 Days
• Field of Search: 370/360, 370/362, 370/363, 370/364, 370/366, 370/367, 370/368, 370/537, 370/538, 370/539, 370/540, 370/541, 370/466, 370/395, 370/389, 370/396, 370/398, 370/352, 370/353, 370/354, 370/355, 370/356
• US Class Current: 370/474
• CPC Class Codes: H04J 2203/0048 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04J 2203/0089 Multiplexing, e.g. coding, scrambling, SONET
• CPC Class Codes: H04L 12/6402 Hybrid switching fabrics
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A system for interfacing with a data bus is provided. The system includes an egress bus data interface that can receive a single incoming stream of STM data and ATM data. The egress bus data interface transmits a single incoming stream of STM data, and a single incoming stream of ATM. The system also includes an ingress bus data interface. The ingress bus interface receives a single outgoing stream of STM data and a single outgoing stream of ATM data. The STM data and ATM data are transmitted in a single outgoing stream.

Claims

1. A system for interfacing with a data bus comprising:

an egress bus data interface operable to receive a pair of single incoming streams, each pair of single incoming streams including both synchronous transfer mode data and asynchronous transfer mode data, the egress bus data interface operable to separately generate and transmit a first incoming stream of synchronous transfer mode data and a second incoming stream of asynchronous transfer mode data each from a selected one of the pair of single incoming streams, wherein the first incoming stream of synchronous transfer mode data is generated from either a same one or a different one of the pair of single incoming streams used to generate the second incoming stream of asynchronous transfer mode data; and

an ingress bus data interface coupled to the egress bus data interface, the ingress bus data interface operable to receive a first outgoing stream of synchronous transfer mode data and a second outgoing stream of asynchronous transfer mode data and to transmit a pair of single outgoing streams each including both synchronous transfer mode data and asynchronous transfer mode data therefrom.

2. The system of claim 1 wherein the egress bus data interface is further operable to receive idle data in each of the pair of single incoming streams of synchronous transfer mode data and asynchronous transfer mode data.

3. The system of claim 1 wherein the ingress bus data interface is further operable to transmit idle data in each of the pair of single outgoing streams of synchronous transfer mode data and asynchronous transfer mode data.

4. The system of claim 1 wherein the pair of single incoming streams of synchronous transfer mode data and asynchronous transfer mode data each comprise a plurality of egress bus frames.

5. The system of claim 1 wherein the pair of single incoming streams each including synchronous transfer mode data and asynchronous transfer mode data each comprise a frame header and a plurality of bus slots.

6. The system of claim 4 wherein each egress bus frame comprises a 32-byte frame header and a plurality of 64-byte bus slots.

7. The system of claim 1 wherein the first incoming stream of synchronous transfer mode data comprises a plurality of synchronous transfer mode datagrams.

8. The system of claim 1 wherein the second incoming stream of asynchronous transfer mode data comprises a plurality of proprietary packet layer datagrams.

9. The system of claim 8 wherein each proprietary packet layer datagram comprises an proprietary packet layer header, an proprietary packet layer payload, and eight bits of CRC-8 data.

10. The system of claim 1 wherein the pair of single outgoing streams each including synchronous transfer mode data and asynchronous transfer mode data each comprise a plurality of ingress bus frames.

11. The system of claim 1 wherein the pair of single outgoing streams each including synchronous transfer mode data and asynchronous transfer mode data each comprise a frame header and a plurality of bus slots.

12. The system of claim 10 wherein each ingress bus frame comprises a 32-byte frame header and a plurality of 64-byte bus slots.

13. The system of claim 1 wherein the first outgoing stream of synchronous transfer mode data comprises a plurality of synchronous transfer mode datagrams.

14. The system of claim 1 wherein the second outgoing stream of asynchronous transfer mode data comprises a plurality of proprietary packet layer datagrams.

15. The system of claim 14 wherein each proprietary packet layer datagram comprises an proprietary packet layer header, an proprietary packet layer payload, and eight bits of CRC-8 data.

16. A system for interfacing with a data bus comprising:

an egress bus data interface operable to receive a pair of single incoming streams of synchronous transfer mode data, asynchronous transfer mode data, and idle data, the egress bus data interface operable to generate and transmit a first incoming stream of synchronous transfer mode data and a second incoming stream of asynchronous transfer mode data each from a selected one of the pair of single incoming streams, wherein the first incoming stream of synchronous transfer mode data is generated from either a same one or a different one of the pair of single incoming streams used to generate the second incoming stream of asynchronous transfer mode data;

an ingress bus data interface coupled to the egress bus data interface, the ingress bus data interface operable to receive a first outgoing stream of synchronous transfer mode data and a second outgoing stream of asynchronous transfer mode data, the ingress bus data interface operable to transmit a pair of single outgoing streams each having synchronous transfer mode data, asynchronous transfer mode data, and idle data; and

wherein the pair of single incoming streams and the pair of single outgoing streams further include a frame header and a plurality of bus slots.

17. A system for interfacing with a data bus comprising:

an egress bus data interface operable to receive a plurality of egress bus frames over a pair of incoming streams and to separately generate and transmit incoming synchronous transfer mode datagrams and incoming proprietary packet layer datagrams each from a selected one of the pair of incoming streams, wherein the incoming synchronous transfer mode datagrams are generated from either a same one or a different one of the pair of incoming streams used to generate the proprietary packet layer datagrams; and

an ingress bus data interface operable to receive a plurality of outgoing synchronous transfer mode datagrams and a plurality of outgoing proprietary packet layer datagrams and to transmit a plurality of ingress bus frames therefrom over a pair of outgoing streams.

18. The system of claim 17 comprising:

each of the egress bus frames further comprises;

a 32-byte frame header; and

a plurality of 64-byte bus slots; and

each of the ingress bus frames further comprises;

a 32-byte frame header; and

a plurality of 64-byte bus slots.

19. A system for interfacing with a data bus comprising:

an egress bus data interface operable to receive a plurality of egress bus frames and to transmit incoming synchronous transfer mode datagrams and incoming internal proprietary packet layer datagrams therefrom; and

an ingress bus data interface operable to receive a plurality of outgoing synchronous transfer mode datagrams and a plurality of outgoing internal proprietary packet layer datagrams and to transmit a plurality of ingress bus frames therefrom, each of the plurality of ingress bus frames carrying both synchronous transfer mode data and asynchronous transfer mode data in separate datagram formats, wherein the proprietary packet layer datagrams comprise a proprietary packet layer header, a proprietary packet layer payload, and eight bits of CRC-8 data, the ingress bus data interface operable to provide ingress bus frames to the egress bus data interface for loopback processing.

20. A method for interfacing with a data bus comprising:

receiving a plurality of egress bus frames over a pair of incoming streams;

separating synchronous transfer mode data and asynchronous transfer mode data from each of the egress bus frames of each pair of incoming streams;

selecting one of the pair of incoming streams;

generating and transmitting the synchronous transfer mode data over a first data bus from a selected one of the pair of incoming streams; and

generating and transmitting the asynchronous transfer mode data over a second data bus from a selected one of the pair of incoming streams, wherein the synchronous transfer mode data on the first bus is generated from either a same one or a different one of the pair of incoming streams used to generate the asynchronous transfer mode data on the second bus.

21. The method of claim 20 wherein transmitting the synchronous transfer mode data over a first data bus comprises transmitting a plurality of synchronous transfer mode datagrams over the first data bus.

22. The method of claim 20 wherein transmitting the asynchronous transfer mode data over a second data bus comprises transmitting a plurality of proprietary packet layer datagrams over the second data bus.

23. A method for interfacing with a data bus comprising:

receiving synchronous transfer mode data over a first data bus;

receiving asynchronous transfer mode data over a second data bus;

combining the synchronous transfer mode data and asynchronous transfer mode data into a plurality of ingress bus frames;

transmitting the plurality of ingress bus frames over separate ingress buses, each of the plurality of ingress bus frames carrying both synchronous transfer mode data and asynchronous transfer mode data in separate datagram formats;

providing the ingress bus frames for loopback processing;

wherein combining the synchronous transfer mode data and the asynchronous transfer mode data further comprises;

determining whether a predetermined bus slot of the ingress bus frames is to carry a synchronous transfer mode datagram or an internal proprietary packet layer datagram;

transmitting a synchronous transfer mode datagram in the predetermined bus slot if the bus slot is to carry synchronous transfer mode data; and

transmitting an internal proprietary packet layer datagram in the predetermined bus slot if the bus slot is to carry asynchronous transfer mode data.

24. The method of claim 23 wherein combining the synchronous transfer mode data and the asynchronous transfer mode data further comprises:

determining whether a predetermined bus slot of the ingress bus frame must contain a synchronous transfer mode datagram or an iMPAX packet layer datagram;

transmitting a synchronous transfer mode datagram in the predetermined bus slot if the bus slot must contain synchronous transfer mode data; and

transmitting an iMPAX packet layer datagram in the predetermined bus slot if the bus slot must contain asynchronous transfer mode data.