Digital modulator

• US 6,320,912 B1
• Filed: 07/27/1998
• Issued: 11/20/2001
• Est. Priority Date: 07/30/1997
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Baba, Satoshi
• Primary Examiner(s): Ghayour, Mohammad H.
• Application Number:
  US09/123,044
• Time in Patent Office: 1,212 Days
• Field of Search: 375/264, 375/278, 375/285, 375/286, 375/296, 370/358, 370/360, 455/63, 455/68, 332/104, 332/107, 332/123, 332/126, 332/159
• US Class Current: 375/264
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence

Abstract

There is disclosed a digital modulator whose modulation parameter can be controlled and in which modulation data or modulated signals are prevented from generating interference signals with adjoining circuits through control when power supply is turned on or system is changed. The digital modulator has a device for detecting that the power supply is turned on, and the transmission data is modulated with fixed data in response to an output of the detecting device for a time required for completing a required system constitution setting. The digital modulator also has a device for detecting the presence of the control for changing the system after the power supply is turned on. In response to an output of the detecting device, modulation is performed with the fixed data for a time from the start till the completion of the setting with a predetermined time added thereto.

Claims

1. A digital modulator for modulating transmission data in a required band, comprising:

means for outside control of a modulation parameter; and

switching means for modulation with fixed data instead of said transmission data only for a predetermined time when turning on of a power supply of said digital modulator is detected or when a signal for said outside control is detected.

2. The digital modulator according to claim 1 wherein said predetermined time is a time which is obtained by adding a setting time (Ts) of said modulation parameter, a switching time (Tc) of said switching means and a power-on time (Tp) when said turning on of the power supply is detected or a time which is obtained by adding the setting time of said modulation parameter and the switching time of said switching means when said outside control signal is detected.

3. The digital modulator according to claim 1, the switching means comprising:

a power-on detecting circuit for detecting that the power supply of said digital modulator is turned on;

a control signal latch circuit for detecting that a control signal for controlling the modulation parameter is entered;

an AND circuit for detecting that an output of either said power-on detecting circuit or said control signal latch circuit is generated;

a timer circuit for delaying an output of said AND circuit by a predetermined time; and

a switch for switching data to the fixed data or said transmission data based on an output of said timer circuit when the power supply is turned on or when the modulation parameter is changed.

4. The digital modulator according to claim 1 wherein said outside control means changes the modulation parameter which is a degree of modulation system, a data speed of modulation data and coefficient of a digital filter based on a clock signal obtained by controlling the number of frequency division of a reference clock from outside.

5. The digital modulator according to claim 4 wherein said frequency division is performed by a first frequency divider for controlling a data speed of said digital modulator and a second frequency divider for controlling a coefficient of a waveform shaping filter.

6. The digital modulator according to claim 5 wherein said first frequency divider sets said frequency division number to 1/(N•

S), where N=1,2,3,4 . . . and S=1,2,4,8 . . . .

7. The digital modulator according to claim 5 wherein said second frequency divider sets said frequency division number to 1/M, in which M is a positive integer.

8. The digital modulator according to claim 1 wherein digital modulator is a quadrature amplitude modulator and degree of said digital modulator is 2^2M.

9. The digital modulator according to claim 1, said switching means comprising:

a power-on detecting circuit for detecting that the power supply of said digital modulator is turned on;

a control signal latch circuit for detecting that a control signal for controlling the modulation parameter is entered;

an AND circuit for detecting that an output of either said power-on detecting circuit or said control signal latch circuit is generated;

a timer circuit for delaying an output of said AND circuit by a predetermined time; and

a flip-flop connected to said transmission data for outputting a held data value just before operation of said timer circuit based on an output of said timer circuit when the power supply is turned on or when the modulation parameter is changed.

10. The digital modulator according to claim 1, said switching means comprising:

a power-on detecting circuit for detecting that the power supply of said digital modulator is turned on;

a control signal latch circuit for detecting that a control signal for controlling the modulation parameter is entered;

an AND circuit for detecting that an output of either said power-on detecting circuit or said control signal latch circuit is generated;

a timer circuit for delaying an output of said AND circuit by a predetermined time; and

an inhibiting circuit for stopping sampling of a D/A converter for digital-analog converting said transmission data based on an output of said timer circuit when the power supply is turned on or when the modulation parameter is changed.

20. The digital modulator according to claim 1 wherein said fixed data are set to digital bit paterns which provide a modulation average output level at a multi-level quadrature amplitude modulation.

11. A digital modulator for modulating transmission data in a required band, comprising:

means for outside control of a modulation parameter;

a digital signal processor for converting an input data signal to two orthogonal strings of parallel data;

a switching circuit for inputting said parallel data and fixed data for each of said strings and switching in such a manner that said fixed data is outputted instead of said parallel data only for a predetermined time when a power supply of said digital modulator is turned on or when a signal for said outside control is detected;

a waveform shaping filter for shaping a waveform of each output of said switching circuit;

a D/A converter for receiving each output of said waveform shaping filter for digital-analog conversion;

a low-pass filter for receiving each output of said D/A converter and removing a high-frequency noise;

an orthogonal modulator for orthogonally modulating each output of said low-pass filter on a carrier frequency; and

an amplifier for amplifying an output of said orthogonal modulator to a predetermined output.

12. The digital modulator according to claim 11 wherein said predetermined time is a time which is obtained by adding a setting time of said modulation parameter, a switching time of said switching means and a time required for stabilizing the power supply when said turning on of the power supply is detected or a time which is obtained by adding the setting time of said modulation parameter and the switching time of said switching means when said outside control signal is detected.

13. The digital modulator according to claim 11 wherein said outside control means changes the modulation parameter which is a degree of modulation system, a data speed of modulation data and coefficient of a digital filter based on a clock signal obtained by controlling the number of frequency division of a reference clock from outside.

14. The digital modulator according to claim 11 wherein said frequency division is performed by a first frequency divider for controlling a bit number of data of said digital modulator and a second frequency divider for controlling a coefficient of the waveform shaping filter.

15. The digital modulator according to claim 14 wherein said first frequency divider sets said frequency division number to 1/(N•

S) , where N=1,2,3 . . . and S=1,2,4,8 . . . .

16. The digital modulator according to claim 14 wherein said second frequency divider sets said frequency division number to 1/M, in which M is a positive integer.

17. The digital modulator according to claim 11 wherein digital modulator is a quadrature amplitude modulator and degree of said digital modulator is 2^2M.

18. The digital modulator according to claim 11, said switching means comprising:

a power-on detecting circuit for detecting that the power supply of said digital modulator is turned on;

a control signal latch circuit for detecting that a control signal for controlling the modulation parameter is entered;

an AND circuit for detecting that an output of either said power-on detecting circuit or said control signal latch circuit is generated;

a timer circuit for delaying an output of said AND circuit by a predetermined time; and

a flip-flop connected to said transmission data for outputting a held data value just before operation of said timer circuit based on an output of said timer circuit when the power supply is turned on or when the modulation parameter is changed.

19. The digital modulator according to claim 11, said switching means comprising:

a power-on detecting circuit for detecting that the power supply of said digital modulator is turned on;

a control signal latch circuit for detecting that a control signal for controlling the modulation parameter is entered;

an AND circuit for detecting that an output of either said power-on detecting circuit or said control signal latch circuit is generated;

a timer circuit for delaying an output of said AND circuit by a predetermined time; and

an inhibiting circuit for stopping sampling of a D/A converter for digital-analog converting said transmission data based on an output of said timer circuit when the power supply is turned on or when the modulation parameter is changed.

21. The digital modulator according to claim 11 wherein said fixed data are set to digital bit paterns which provide a modulation average output level at a multi-level quadrature amplitude modulation.