Fast acquisition clock recovery using a directional frequency-phase detector

• US 6,320,921 B1
• Filed: 09/25/1998
• Issued: 11/20/2001
• Est. Priority Date: 09/29/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gu, Richard X.
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/160,905
• Time in Patent Office: 1,152 Days
• Field of Search: 375/376, 375/375, 375/374, 375/294, 375/362, 375/327, 327/147, 327/148, 327/149, 327/156, 327/157, 327/158, 327/236, 327/244, 329/307
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A phase-locked loop circuit is disclosed. The phase-locked loop circuit includes a fundamental/quadrature phase comparator circuit (12) that compares an input bitstream (IN) to fundamental and quadrature phases of an output clock signal (CLK, CLKQ), to generate logic signals (I1, I2) corresponding to the state of the output clock signal phases at the time of each transition of the input bitstream. Compare logic (44) in the fundamental/quadrature phase comparator circuit (12) generates anticlockwise (A) and clockwise (C) signals to a state machine (14), in response to the logic signals (I1, I2) varying from a prior state (X1, X2) in opposing directions in a sequence; the sequence and directions are indicative of the polarity of the error frequency between the input bitstream and the output clock signal. Beginning with the first comparison and in response to the anticlockwise (A) and clockwise (C) signals, the state machine (14) issues a high gain charge or discharge signal (UPC, DNC) to a charge pump filter (20), to raise or lower the voltage (V_n) at a capacitor (25) and thus increase or decrease the oscillation frequency of a voltage-controlled oscillator (30) that generates the output clock signal (CLK). This charge or discharge operation continues until the opposite one of the anticlockwise (A) and clockwise (C) signals is produced by the compare logic (44), at which time the state machine begins issuing lower gain discharge or charge signals (DND, UPD) to correct the output clock frequency in the opposite direction, in a fine correction manner.

Claims

1. A phase-locked loop, comprising:

a voltage-controlled oscillator, for generating an output clock signal having a frequency responsive to a control voltage;

a charge pump circuit for generating the control voltage in response to charge/discharge control signals; and

a frequency/phase detector circuit, comprising;

a phase comparator circuit, having a first input for receiving an input signal, having a feedback input for receiving the output clock signal, for generating first and second indicator signals corresponding to the phase comparator circuit detecting first and second polarities of an error frequency between the input signal and the output clock signal; and

sequential logic, for receiving indicator signals from the phase comparator circuit, and for generating a first charge/discharge control signal for controlling the charge pump circuit to change the control voltage applied to the voltage-controlled oscillator in a first direction at a first rate responsive to receiving a first one of the first and second indicator signals, and for then generating a second charge/discharge control signal for controlling the charge pump circuit to change the control voltage applied to the voltage-controlled oscillator in a second direction, at a second rate that is lower than the first rate, responsive to receiving the other one of the first and second indicator signals.

2. The phase-locked loop of claim 1, wherein the phase comparator circuit comprises:

a delay stage having an input receiving a fundamental phase of the output clock signal and for generating a quadrature phase of the output clock signal;

circuitry for generating a pair of current logic signals corresponding to states of the fundamental and quadrature phases of the output clock signal responsive to receiving a transition of the input signal; and

compare logic for comparing the pair of current logic signals to a pair of prior logic signals, corresponding to states of the fundamental and quadrature phases of the output clock signal at a previous transition of the input signal, and for generating first and second direction indicator signals responsive to the direction of change of the current logic signals relative to the prior logic signals according to a predetermined sequence.

3. The phase-locked loop of claim 2, wherein the sequential logic is for:

in a first state, applying a high-gain charge signal to the charge pump circuit;

in a second state, applying a high-gain discharge signal to the charge pump circuit;

in a third state, applying a low-gain signal to the charge pump circuit; and

in a fourth state, applying a low-gain discharge signal to the charge pump circuit;

wherein the sequential logic enters into and remains in the first state responsive to receiving a first instance of the first direction indicator signal from the compare logic, and enters the fourth state responsive to then receiving the second indicator signal from the compare logic;

and wherein the sequential logic enters into and remains in the second state responsive to receiving a first instance of the second direction indicator signal from the compare logic, and then enters the third state responsive to then receiving the first indicator signal from the compare logic.

4. The phase-locked loop of claim 3, wherein the charge pump circuit comprises

a capacitor;

a first transistor, having a conduction path coupled between a power supply voltage and the capacitor, and having a control electrode coupled to receive the high-gain charge signal;

a second transistor, having a conduction path coupled between the power supply voltage and the capacitor, and having a control electrode coupled to receive the low-gain signal, the second transistor having substantially weaker drive characteristics than the first transistor;

a third transistor, having a conduction path coupled between a reference voltage and the capacitor, and having a control electrode coupled to receive the high-gain discharge signal; and

a fourth transistor, having a conduction path coupled between the reference voltage and the capacitor, and having a control electrode coupled to receive the low-gain discharge signal, the fourth transistor having substantially weaker drive characteristics than the third transistor.

5. The phase-locked loop of claim 3, wherein the sequential logic comprises:

combinational logic, for receiving the first and second direction indicator signals and for receiving a plurality of feedback signals and for generating an output signal indicating whether one of the first and second direction indicator signals has been received since initialization;

a delay circuit, for generating a delayed signal based upon an occurrence of either of the first and second indicator signals;

a first latch for storing the output of the combinational logic, and having a clock input receiving the delayed signal;

second and third latches, for storing the state of the first and second indicator signals, respectively, each having a clock input receiving the delayed signal; and

output logic, coupled to outputs of the first, second, and third latches, for generating the high-gain charge and discharge signals and the low-gain charge and discharge signals.

6. The phase-locked loop of claim 2, wherein the phase comparator circuit further comprises:

next state logic, coupled to inputs of the compare logic, for generating prior logic signals for use in connection with a next transition of the input signal.

7. A method of recovering a clock signal from an input bitstream, comprising the steps of:

initializing an output clock signal to an initial frequency;

periodically comparing the input bitstream to the initialized output clock signal to determine whether a frequency relationship therebetween is of a first or second polarity;

responsive to the comparing step determining that the frequency relationship is of the first polarity, controlling a voltage-controlled oscillator to change the frequency of the output clock signal in a first direction at a first rate;

then, responsive to the comparing step determining that the frequency relationship is of the second polarity, controlling the voltage-controlled oscillator to change the frequency of the output clock signal in a second, opposite, direction at a second rate that is less than the first rate.

8. The method of claim 7, further comprising:

after the step of controlling the voltage-controlled oscillator to change the frequency of the output clock signal in the second direction, controlling the voltage-controlled oscillator to change the frequency of the output clock signal in the first direction, at the second rate, responsive to the comparing step determining that the frequency relationship is of the first polarity.

9. The method of claim 7, wherein the steps of controlling the voltage-controlled oscillator comprise selectively charging and discharging a capacitor in a charge pump.

10. The method of claim 9, wherein the step of controlling the voltage-controlled oscillator in the first direction at the first rate comprises turning on one of a plurality of high-drive transistors.

11. The method of claim 10, wherein the step of controlling the voltage-controlled oscillator in the second direction at the second rate comprises turning on one of a plurality of low-drive transistors, the low-drive transistors having relatively weak drive characteristics relative to crresponding ones of the plurality of high-drive transistors.

12. The method of claim 7, wherein the comparing step comprises:

generating a quadrature phase of the output clock signal from a fundamental phase thereof;

responsive to each transition of the input bitsteam, generating a pair of current logic signals corresponding to the state of the fundamental and quadrature phases of the output clock signal at the time of the transition of the input bitstream;

comparing the pair of current logic signals to a pair of prior logic signals, the pair of prior logic signals corresponding to the state of the fundamental and quadrature phases of the output clock signal at the time of a prior transition of the input bitstream;

responsive to the comparing step detecting rotation of the current logic signals from the prior logic signals in a first direction along a predetermined sequence, issuing a first direction indicator signal; and

responsive to the comparing step detecting rotation of the current logic signals from the prior logic signals in a second direction along the predetermined sequence, issuing a second direction indicator signal.