Radiotelephone receiver and method with improved dynamic range and DC offset correction

• US 6,321,073 B1
• Filed: 01/31/2000
• Issued: 11/20/2001
• Est. Priority Date: 01/31/2000
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Thorson, Dean E., Luzzatto, Ariel, Luz, Yuda Y.
• Primary Examiner(s): Maung, Nay
• Assistant Examiner(s): PERSINO, RAYMOND B
• Application Number:
  US09/495,162
• Time in Patent Office: 659 Days
• Field of Search: 455/232.1, 455/234.1, 455/234.2, 455/235.1, 455/236.1, 455/239.1, 455/240.1, 455/241.1, 455/245.1, 455/245.2, 455/249.1, 455/251.1 , 455/252.1, 455/253.2, 330/129, 330/131, 330/278, 330/279, 330/284, 330/285, 375/345, 375/317, 375/319
• US Class Current: 455/239.1
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

An automatic gain control apparatus (106) and method for a radiotelephone receiver employs stored inverse transfer function data (400) of the radiotelephone receiver and a gain estimation circuit (200). The gain estimation circuit (200) estimates the input power of received signal (103) and determines a required gain based on a nonlinear portion of the inverse transfer function data (400) of the radiotelephone receiver to provide an improved dynamic range of the receiver. The apparatus and method performs convergence within one iteration to perform fast gain control. In addition, if desired, a DC offset compensation circuit, such as a feedforward DC offset compensation circuit (202), compensates the digital representation of the input signal for use by the gain estimation circuit (200).

Claims

1. An automatic gain control apparatus for a radiotelephone receiver comprising:

memory containing data representing a transfer function of the radio telephone receiver;

a gain estimation circuit, operatively coupled to the memory, that estimates input power and determines a required gain for an input signal based on a non-linear portion of the data representing the transfer function; and

a DC offset compensation circuit operatively coupled to the gain estimation circuit, the DC offset compensation circuit comprising;

a circuit for calculating a mean value of the signal having an in-phase (I) component and a quadrature (Q) component;

an in-phase DC compensation circuit for calculating a DC offset error for the I component;

a quadrature DC compensation circuit for calculating a DC offset error for the Q component, wherein the DC offset error for the I component and the DC offset error for the Q component are subtracted from the mean value of the signal; and

a first analog to digital converter coupled to the circuit for calculating a mean value of the signal, wherein the first analog to digital converter receives the I component and produces a first digital I component containing 8 bits and a second digital I component containing 4 bits and wherein the 4 bits are a subset of the 8 bits.

2. The apparatus of claim 1 wherein the data representing the transfer function of the radio telephone receiver includes data representing an inverse of a transfer function of the radiotelephone receiver.

3. The apparatus of claim 2 wherein the data representing the inverse of the transfer function is in the form of a pre-stored table.

4. The apparatus of claim 1 including a plurality of gain stages and wherein the gain estimation circuit simultaneously adjusts the gain on all of the plurality of stages based on the required gain for the input signal.

5. The apparatus of claim 4 including memory containing a gain assignment look up table to set a gain control for each of the plurality of gain stages.

6. The apparatus of claim 1 including a comparator operatively coupled to compare a gain estimate based on the non-linear data from memory, to set point data to determine an amount of adjustment for a gain stage.

7. The automatic gain control apparatus of claim 1 wherein the DC offset compensation circuit further comprises a second analog to digital converter coupled to the circuit for calculating a mean value of the signal, wherein the second analog to digital converter receives the Q component and produces a first digital Q component containing 8 bits and a second digital Q component containing 4 bits and wherein the 4 bits are a subset of the 8 bits.

8. The automatic gain control apparatus of claim 1 wherein the 4 bits are a center 4 bits of the 8 bits.

9. The automatic gain control apparatus of claim 1 wherein the circuit for calculating the mean value of the signal comprises:

a first squaring stage for producing a first squared value of the I component of the signal;

a second squaring stage for producing a second squared value of the Q component of the signal;

a first summer for adding the first and second squared values;

a memory for storing a sum of the first and second squared values; and

a circuit for computing a mean value of the sum of the first and second squared values for a predetermined amount of samples of the signal.

10. The automatic gain control apparatus of claim 9 further comprising:

a first absolute value stage coupled to the first squaring stage for producing an absolute value of the I component; and

a second absolute value stage coupled to the second squaring stage for producing an absolute value of the Q component.

11. The automatic gain control apparatus of claim 1 wherein the in-phase DC compensation circuit comprises:

a memory for storing samples of the I component;

a summer coupled to the memory for adding contents of the memory to a current I component sample;

a circuit for computing a mean value of the I component samples for a predetermined amount of samples of the signal; and

a squaring stage for squaring the mean value of the I component, thereby producing the DC offset error for the I component.

12. The automatic gain control apparatus of claim 1 wherein quadrature DC compensation circuit comprises:

a memory for storing samples of the Q component;

a summer coupled to the memory for adding contents of the memory to a current Q component sample;

a circuit for computing a mean value of the Q component samples for a predetermined amount of samples of the signal; and

a squaring stage for squaring the mean value of the Q component, thereby producing the DC offset error for the Q component.

13. Automatic gain control method for a radiotelephone receiver comprising the steps of:

storing data representing a transfer function of the radio telephone receiver;

converting the I component to a first digital I component containing 8 bits and a second digital I component containing 4 bits, wherein the 4 bits are a subset of the 8 bits;

converting the Q component to a first digital Q component containing 8 bits and a second digital Q component containing 4 bits, wherein the 4 bits are a subset of the 8 bits;

calculating a mean value of an input signal having an in-phase (I) component and a quadrature (Q) component;

calculating a DC offset squared error for the I component;

calculating a DC offset squared error for the Q component, subtracting the DC offset squared error for the I component and the DC offset error for the Q component from the mean value of the input signal; and

estimating input power and determining a required gain for the input signal based on a non-linear portion of the data representing the transfer function.

14. The method of claim 13 wherein the data representing the transfer function of the radio telephone receiver includes data representing an inverse of the transfer function.

15. The method of claim 14 wherein the data representing the inverse of the transfer function is in the form of a table.

16. The method of claim 13 including the step of simultaneously adjusting the gain on all of the plurality of stages based on the required gain for the input signal.

17. The method of claim 16 including storing a gain assignment look up table to set a gain control for each of the plurality of gain stages.

18. The method of claim 13 including the step of comparing a gain estimate based on the non-linear data from memory, to set point data to determine an amount of adjustment for a gain stage.

19. The method of claim 13 wherein the step of calculating a mean value of the signal comprises:

producing a first squared value of the I component of the signal;

producing a second squared value of the Q component of the signal;

summing the first and second squared values to produce a first sum;

adding the first sum to contents of a memory to produce a second sum;

storing the second sum in the memory;

repeating the above steps for a predetermined amount of samples of the signal; and

computing a mean value of the second sum for the predetermined amount of samples of the signal.

20. The method of claim 13 wherein the step of calculating a DC offset error for the I component comprises:

adding a current I component to contents of a memory to produce a first sum;

storing the first sum in the memory;

repeating the above steps for a predetermined amount of samples of the signal;

computing a mean value for the first sum for the predetermined amount of samples of the signal; and

squaring the mean value of the first sum, thereby producing the DC offset error for the I component.

21. The method of claim 13 wherein the step of calculating a DC offset error for the Q component comprises:

adding a current Q component to contents of a memory to produce a first sum;

storing the first sum in the memory;

repeating the above steps for a predetermined amount of samples of the signal;

computing a mean value for the first sum for the predetermined amount of samples of the signal; and

squaring the mean value of the first sum, thereby producing the DC offset error for the Q component.