Method and apparatus for restricting memory access

• US 6,321,314 B1
• Filed: 06/09/1999
• Issued: 11/20/2001
• Est. Priority Date: 06/09/1999
• Status: Expired due to Term

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Van Dyke, Korbin S.
• Primary Examiner(s): Lane, Jack A.
• Application Number:
  US09/328,333
• Time in Patent Office: 895 Days
• Field of Search: 711/163
• US Class Current: 711/163
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect

Abstract

A method and apparatus for restricting memory access includes processing that begins by monitoring memory access requests. When one of the memory access requests is requesting access to restricted memory, determining the mode of operation of the processor. Note that the mode of operation of the processor may be a system special operation (i.e., operations internal to the operation of the computing system that are beyond access of computing system users and programmers), non-system special operations, or a valid response to a restricted memory access request. When the mode of operation is non-system special and the memory access is requesting access to restricted memory, the memory access request is modified. The processing then continues by providing a response in accordance with the modified memory access request.

Claims

1. A method for restricting memory access, the method comprises the steps of:

a) monitoring memory access requests;

b) when one of the memory access requests is addressing restricted memory, determining mode of operation of a processor;

c) when the mode of the operation of the processor is a non-system special operation modifying the one of the memory access requests to produce a modified memory access request; and

d) providing a response in accordance with the modified memory access request.

2. The method of claim 1 further comprises, when the mode of operation of the processor is a system special operation, allowing access to the restricted memory.

3. The method of claim 1, wherein steps (a) and (c) further comprise:

comparing an address of the one of the memory access requests with a restricted memory threshold address;

when the comparing is unfavorable, modifying the memory access request.

4. The method of claim 3, wherein steps (c) and (d) further comprise:

modifying a read memory access request to a default data request; and

providing default data.

5. The method of claim 3, wherein steps (c) and (d) further comprise:

modifying a write memory access request to a null request; and

providing a transaction complete indication.

6. The method of claim 1, wherein the one of the memory access requests includes an extended linear address having a linear address and an address extension.

7. The method of claim 6, wherein step (c) further comprises:

determining whether the one of the memory access requests has a corresponding entry in a translation look aside buffer;

when the one of the plurality of memory access requests does not have a corresponding entry in the translation look aside buffer, providing the linear address to one of a plurality of exception handlers based on the address extension;

determining whether the one of the plurality of exception handlers produces a valid translation look aside buffer entry; and

when the one of the plurality of exception handlers did not produce the valid translation look aside buffer entry, producing a modified translation look aside buffer entry.

8. The method of claim 7, wherein step (d) further comprises:

utilizing the modified translation look aside buffer entry to produce the modified memory access request.

9. The method of claim 7, wherein the determining whether the one of the plurality of exception handlers produces the valid translation look aside buffer entry is performed by a processor register.

10. The method of claim 7, wherein the determining whether the one of the plurality of exception handlers produces the valid translation look aside buffer entry is performed the one of the plurality of exception handlers.

11. A method for restricting memory access, the method comprises the steps of:

a) monitoring memory access requests;

b) when one of the memory access requests is addressing restricted memory, allowing access to the restricted memory if one of the memory access requests is a system special operation, otherwise modifying the one of the memory access requests to produce a modified memory access request; and

c) providing a response in accordance with the modified memory access request.

12. The method of claim 11, wherein steps (a) and (b) further comprise:

comparing an address of the one of the memory access requests with a restricted memory threshold address;

when the comparing is unfavorable, modifying the memory access request.

13. The method of claim 12, wherein step (c) further comprises:

modifying a read memory access request to a default data request; and

providing default data.

14. The method of claim 12, wherein step (c) further comprises:

modifying a write memory access request to a null request; and

providing a transaction complete indication.

15. A memory manager that restricts access to memory, the memory manager comprises:

a processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to (a) monitor memory access requests;

(b) determine mode of operation of a processor when one of the memory access requests is addressing restricted memory;

(c) modify the one of the memory access requests to produce a modified memory access request when the mode of the operation of the processor is a non-system special operation; and

(d) provide a response in accordance with the modified memory access request.

16. The memory manager of claim 15, wherein the memory further comprises operational instructions that cause the processing module to allow access to the restricted memory when the mode of operation of the processor is a system special operation.

17. The memory manager of claim 15, wherein the memory further comprises operational instructions that cause the processing module:

to determine the mode of operation of the processor by comparing an address of the one of the memory access requests with a restricted memory threshold address;

to monitor the memory access requests by modifying the memory access request when the comparing is unfavorable.

18. The memory manager of claim 15, wherein the memory further comprises operational instructions that cause the processing module:

to modify the one of the memory access requests by modifying a read memory access request to a default data request; and

to provide the response by providing default data.

19. The memory manager of claim 15, wherein the memory further comprises operational instructions that cause the processing module:

to modify the one of the memory access requests by modifying a write memory access request to a null request; and

to provide the response by providing a transaction complete indication.

20. The memory manager of claim 15, wherein the one of the plurality of memory access requests includes an extended linear address having a linear address and an address extension.

21. The memory manager of claim 15, wherein the memory further comprises operational instructions that cause the processing module to determine when one of the memory access requests is addressing restricted memory by:

determining whether the one of the plurality of memory access requests has a corresponding entry in a translation look aside buffer;

when the one of the plurality of memory access requests does not have a corresponding entry in the translation look aside buffer, providing the linear address to one of a plurality of exception handlers based on the address extension;

determining whether the one of the plurality of exception handlers produce a valid translation look aside buffer entry; and

when the one of the plurality of exception handlers did not produce the valid translation look aside buffer entry, producing a modified translation look aside buffer entry.

22. The memory manager of claim 21, wherein the memory further comprises operational instructions that cause the processing module to modify the one of the memory access requests by:

utilizing the modified translation look aside buffer entry to produce the modified memory access request.

23. A memory manager that restricts access to memory, the memory manager comprises:

a processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to (a) monitor memory access requests;

(b) allow access to restricted memory when the one of the memory access requests is a system special operation, otherwise modify the one of the memory access requests to produce a modified memory access request when one of the memory access requests is addressing restricted memory; and

(c) provide a response in accordance with the modified memory access request.

24. The memory manager of claim 23, wherein the memory further comprises operational instructions that cause the processing module:

to monitor memory access requests by comparing an address of the one of the memory access requests with a restricted memory threshold address;

to modify the one of the memory access requests by modifying the memory access request when the comparing is unfavorable.

25. The memory manager of claim 23, wherein the memory further comprises operational instructions that cause the processing module to provide the response by:

modifying a read memory access request to a default data request; and

providing default data.